Fairchild Semiconductor DM74164N, DM74164CW Datasheet

© 2000 Fairchild Semiconductor Corporation DS006552 www.fairchildsemi.com

September 1986
Revised February 2000

DM74164 8-Bit Serial In/Parallel Out Shift Registers

DM74164
8-Bit Serial In/Parallel Out Shift Registers

General Description

These 8-bit shift registe rs feature gated serial inpu ts and
an asynchronous clear. A LOW logic level at either serial
input inhibits entry o f th e n ew d ata , an d r ese ts th e first flip­flop to the LOW level at the next clock pulse, thus providing
complete control over incoming data. A HIGH logic level on
either input enables the other input, which will then dete r­mine the state of the first flip-flo p. Data at the serial inputs
may be changed while th e cloc k is HIG H or LOW, but only
information meeting th e setup and ho ld time require ments
will be entered. Clocking occurs on the LOW-to-HIGH level
transition of the clock input. All inputs are diode-clamped to
minimize transmission-line effects.

Features

■ Gated (enable/disable) serial inputs

■ Fully buffered clock and serial inputs

■ Asynchronous clear

■ Typical clock frequency 36 MHz

■ Typical power dissipation 185 mW

Ordering Code:

Connection Diagram Function Table

H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don’t Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
Q

A0

, QB0, QH0 = The level of QA, QB, or QH, respectively, before the

indicated steady-state input conditions were established.

Q

An

, QGn = The level of QA or QG before the most recent ↑ transition of the

clock; indicates a one-bit shift.

Order Number Package Number Package Description

DM74164 N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

Clear Clock A B

Q

AQB

…

Q

H

LXXXLL…L
HLXXQ

A0QB0

…Q

H0

H ↑ HHHQAn…Q

Gn

H ↑ LX L QAn…Q

Gn

H ↑ XL L QAn…Q

Gn

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DM74164

Logic Diagram

Timing Diagram