March 1997
Revised March 1999
74VHCT245A Octal Buffer/Line Driver with 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS500004.prf www.fairchildsemi.com
74VHCT245A
Octal Buffer/Line Driver with 3-ST ATE Outputs
General Description
The VHCT245A is an advanced high speed CM OS octal
bus transceiver fabricated with silicon gate CM OS techn ology. It achieves high speed operati on similar to equival ent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. Th e VHCT245A is i ntended for bidi rectional asynchronous communi cation between data busses.
The direction of data transmission is determined by the
level of the T/R input. The ena ble in put can b e use d to disable the device so that the busses are effectively isolated.
Protection circuits ensu re that 0V to 7V can be applied to
the input and output (No te 1) pins without regard to the
supply voltage. These circ uits prevent device destruction
due to mismatched supply and i nput/output voltage s. This
device can be used to in terface 5V to 3V sys tems an d two
supply systems such as battery back up.
Note 1: Outputs in OFF-State
Features
■ High Speed: tPD = 5.4 ns (typ) at VCC = 5V
■ Power Down Protection on Inputs and Outputs
■ Low Power Dissipation: I
CC
= 4 µA (Max) @ TA = 25°C
■ Pin and Function Compatible with 74HCT245
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code.
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Order Number Package Number Package Description
74VHCT245AM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHCT245ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT245AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT245AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
OE
Output Enable Input
T/R
Transmit/Receive Input
A
0–A7
Side A Inputs or 3-STATE Outputs
B
0–B7
Side B Inputs or 3-STATE Outputs
Inputs
Outputs
OE
T/R
L L Bus B Data to Bus A
L H Bus A Data to Bus B
H X HIGH-Z State