October 1992
Revised March 1999
74VHC74 Dual D-Type Flip-Flop with Preset and Clear
© 1999 Fairchild Semiconductor Corporation DS011505.prf www.fairchildsemi.com
74VHC74
Dual D-Type Flip-Flop with Preset and Clear
General Description
The VHC74 is an advanced high speed CMOS Dual DType Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The sign al leve l a pplie d to the D input is
transferred to the Q outp ut d ur i ng t he p ositive going transition of the CK pulse. CLR
and PR are inde pendent of the
CK and are accomplished by setting the appropriate input
LOW.
An input protection circuit en sures that 0V to 7V can be
applied to the input pins without re gard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. Th is circuit prevents device destruction due to m isma tche d supply
and input voltages.
Features
■ High Speed: f
MAX
= 170 MHz (typ) at TA= 25°C
■ High noise immunity: V
NIH
= V
NIL
= 28% VCC (min)
■ Power down protection is provided on all inputs
■ Low power dissipation: I
CC
= 2 µA (max) at TA= 25°C
■ Pin and function compatible with 74HC74
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code.
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
Note 1: This configuration i s no nst able; tha t is, i t will n ot pe rsis t whe n p re-
set and clear inputs ret urn to their inactive (HIGH ) s t at e.
Order Number Package Number Package Description
74VHC74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
74VHC74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
1
, D
2
Data Inputs
CK
1
, CK
2
Clock Pulse Inputs
CLR
1
, CLR
2
Direct Clear Inputs
PR
1
, PR
2
Direct Preset Inputs
Q
1
, Q1, Q2, Q
2
Output
Inputs Outputs
Function
CLR
PR DCK Q Q
L H X X L H Clear
HLXX H L Preset
L L X X H (Note 1) H (Note 1)
HHL
LH
HHH
HL
HHX
Q
n
QnNo Change