Fairchild Semiconductor 74VHC574SJX, 74VHC574SJ, 74VHC574N, 74VHC574MX, 74VHC574MTCX Datasheet
...
March 1993
Revised April 1999
74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011565.prf www.fairchildsemi.com
74VHC574
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The VHC574 is an advanced high speed CMOS octal fli pflop with 3-STATE output fabricated with silicon gate CMOS
technology. It achieves the high speed opera tion simil ar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. This 8-bit D-type flip-flop is
controlled by a clock input (CP ) and an ou tpu t ena ble i np ut
(OE
). When the OE i nput is HIGH, the e ight outpu ts are in
a high impedance state.
An input protection circuit en sures that 0V to 7V can be
applied to the input pins without re gard to the supply voltage. This device can be used to interface 5V to 3V systems
and two supply systems such as bat tery back up. This cir-
cuit prevents device destruction due to m isma tched supply
and input voltages.
Features
■ High Speed: tPD = 5.6 ns (typ) at VCC = 5V
■ High Noise Immunity: V
NIH
= V
NIL
= 28% VCC (Min)
■ Power Down Protection is provided on all inputs
■ Low Noise: V
OLP
= 0.6V (typ)
■ Low Power Dissipation: I
CC
= 4 µA (Max) @ TA = 25°C
■ Pin and Function Compatible with 74HC574
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC574M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74VHC574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153
74VHC574N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0–D7
Data Inputs
CP Clock Pulse Input
OE
3-STATE Output Enable Input
O
0–O7
3-STATE Outputs
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74VHC574
Functional Description
The VHC574 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Outp ut Enable are com mon to
all flip-flops. The eight flip-flops will store th e state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE
) LOW, the contents of the
eight flip-flops are available at the outputs . When the OE
is
HIGH, the outputs go to th e high impeda nce state. Op eration of the OE
input does not affect t he state of the flip-
flops.
Tr uth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only f or t he understanding of lo gic operations and should not be used to estimate propagation delays.
Inputs Outputs
D
n
CP OE O
n
H
LH
L
LL
XXH Z
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74VHC574
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are valu es beyond whic h the device
may be damaged or ha ve its useful life impaire d. The datab ook specifications should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and o utput/input loading variables. Fairchild does not recommend operation outside databook specifications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Parameter gu aranteed by design.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Voltage (V
IN
) −0.5V to +7.0V
DC Output Voltage (V
OUT
) −0.5V to VCC + 0.5V
Input Diode Current (I
IK
) −20 mA
Output Diode Current ±20 mA
DC Output Current (I
OUT
) ±25 mA
DC V
CC
/GND Current (ICC) ±75 mA
Storage Temperature (T
STG
) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260°C
Supply Voltage (V
CC
)2.0V to +5.5V
Input Voltage (V
IN
)0V to +5.5V
Output Voltage (V
OUT
)0V to V
CC
Operating Temperature (T
OPR
) −40°C to +85°C
Input Rise and Fall Time (t
r
, tf)
V
CC
= 3.3V ± 0.3V 0 ∼ 100 ns/V
V
CC
= 5.0V ± 0.5V 0 ∼ 20 ns/V
Symbol Parameter
V
CC
(V)
TA = 25°CT
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
V
IH
HIGH Level 2.0 1.50 1.50
V
Input Voltage 3.0 − 5.5 0.7 V
CC
0.7 V
CC
V
IL
LOW Level 2.0 0.50 0.50
V
Input Voltage 3.0 − 5.5 0.3 V
CC
0.3 V
CC
V
OH
HIGH Level 2.0 1.9 2.0 1.9 VIN = VIHIOH = −50 µA
Output Voltage 3.0 2.9 3.0 2.9 V or V
IL
4.5 4.4 4.5 4.4
3.0 2.58 2.48
V
IOH = −4 mA
4.5 3.94 3.80 IOH = −8 mA
V
OL
LOW Level 2.0 0.0 0.1 0.1 VIN = VIHIOL = 50 µA
Output Voltage 3.0 0.0 0.1 0.1 V or V
IL
4.5 0.0 0.1 0.1
3.0 0.36 0.44
V
IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
I
OZ
3-STATE 5.5 ±0.25 ±2.5 µAVIN = VIH or V
IL
Output Off-State Current V
OUT
= VCC or GND
I
IN
Input Leakage 0 − 5.5 ±0.1 ±1.0 µAVIN = 5.5V or GND
Current
I
CC
Quiescent Supply 5.5 4.0 40.0 µAVIN = VCC or GND
Current
Symbol Parameter
V
CC
(V)
TA = 25°C
Units Conditions
Typ Limits
V
OLP
(Note 3)
Quiet Output Maximum Dynamic V
OL
5.0 1.0 1.2 V CL = 50 pF
V
OLV
(Note 3)
Quiet Output Minimum Dynamic V
OL
5.0 −0.8 −1.0 V CL = 50 pF
V
IHD
(Note 3)
Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL = 50 pF
V
ILD
(Note 3)
Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL = 50 pF
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