Fairchild Semiconductor 74VHC541SJX, 74VHC541SJ, 74VHC541N, 74VHC541MX, 74VHC541MTCX Datasheet
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August 1993
Revised April 1999
74VHC541 Octal Buffer/Line Driver with 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011639.prf www.fairchildsemi.com
74VHC541
Octal Buffer/Line Driver with 3-ST ATE Outputs
General Description
The VHC541 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissipation.
The VHC541 is an oc tal buffer/line driver designed to be
employed as memory a nd address drivers, clock drivers
and bus oriented transmitter/receivers.
This device is similar in function to the VHC244 while providing flow-through architecture (inputs on opposite side
from outputs). This pinout ar rangement makes this de vice
especially useful as an output port for microprocessors,
allowing ease of layout and greater PC board density.
An input protecti on circuit insures that 0V to 7 V can be
applied to the inp ut pins with out regard to the sup ply voltage. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. Th is circuit prevents device destruction due to m isma tche d supply
and input voltages.
Features
■ High Speed: tPD = 3.5 ns (typ) at VCC = 5V
■ Low power dissipation: I
CC
= 4 µA (max) at TA = 25°C
■ High noise immunity: V
NIH
= V
NIL
= 28% VCC (min)
■ Power down protection is provided on all inputs
■ Low noise: V
OLP
= 0.9V (typ)
■ Pin and function compatible with 74HC541
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code.
Connection Diagram
Pin Descriptions
Logic Symbol
IEEE/IEC
Truth T able
H = HIGH Voltage Level X = Immaterial
L = LOW Voltage Level Z = High Impedance
Order Number Package Number Package Description
74VHC541M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHC541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC541N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Descriptions
OE
1
, OE
2
3-STATE Output Enable Inputs
I
0
- I
7
Inputs
O
0
- O
7
3-STATE Outputs
Inputs Outputs
OE
1
OE
2
I
LLHH
HXXZ
XHXZ
LLLL
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74VHC541
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or ha ve its useful li fe impaire d. The datab ook specifications should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and ou tput/input loading variables. Fairchild does not recom mend operation outside data book specifications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float
DC Electrical Characteristics
Noise Characteristics
Note 3: Paramete r guaranteed by design.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Voltage (V
IN
) −0.5V to +7.0V
DC Output Voltage (V
OUT
) −0.5V to VCC + 0.5V
Input Diode Current (I
IK
) −20 mA
Output Diode Current (I
OK
) ±20 mA
DC Output Current (I
OUT
) ±25 mA
DC V
CC
/GND Current (ICC) ±75 mA
Storage Temperature (T
STG
) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260°C
Supply Voltage ( V
CC
) 2.0V to +5.5V
Input Voltage (V
IN
)0V to +5.5V
Output Voltage (V
OUT
) 0V to V
CC
Operating Temperature (T
OPR
) −40°C to +85°C
Input Rise and Fall Time (t
r
, tf)
V
CC
= 3.3V ±0.3V 0 ∼ 100 ns/V
V
CC
= 5.0V ±0.5V 0 ∼ 20 ns/V
Symbol Parameter
V
CC
(V)
TA = 25°CT
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
V
IH
HIGH Level Input 2.0 1.50 1.50
V
Voltage 3.0 − 5.5 0.7 V
CC
0.7 V
CC
V
IL
LOW Level Input 2.0 0.50 0.50
V
Voltage 3.0 − 5.5 0.3 V
CC
0.3 V
CC
V
OH
HIGH Level Output 2.0 1.9 2.0 1.9 VIN = VIHIOH = −50 µA
Voltage 3.0 2.9 3.0 2.9 V or V
IL
4.5 4.4 4.5 4.4
3.0 2.58 2.48
V
IOH = −4 mA
4.5 3.94 3.80 IOH = −8 mA
V
OL
LOW Level Output 2.0 0.0 0.1 0.1 VIN = VIHIOL = 50 µA
Voltage 3.0 0.0 0.1 0.1 V or V
IL
4.5 0.0 0.1 0.1
3.0 0.36 0.44
V
IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
I
OZ
3-STATE Output 5.5 ±0.25 ±2.5
µA
VIN = VIH or V
IL
Off-State Current V
OUT
= VCC or GND
I
IN
Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAVIN = 5.5V or GND
I
CC
Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND
Symbol Parameter
V
CC
(V)
TA = 25°C
Units Conditions
Typ Limits
V
OLP
Quiet Output Maximum Dynamic 5.0 0.9 1.2
V
CL = 50 pF
(Note 3) V
OL
V
OLV
Quiet Output Minimum Dynamic 5.0 −0.8 −1.0
V
CL = 50 pF
(Note 3) V
OL
V
IHD
Minimum HIGH Level Dynamic 5.0 3.5
V
CL = 50 pF
(Note 3) Input Voltage
V
ILD
Maximum HIGH Level Dynamic 5.0 1.5
V
CL = 50 pF
(Note 3) Input Voltage
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