Fairchild Semiconductor 74VHC4040N, 74VHC4040MX, 74VHC4040MTCX, 74VHC4040MTC, 74VHC4040MSCX Datasheet
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August 1993
Revised April 1999
74VHC4040 12-Stage Binary Counter
© 1999 Fairchild Semiconductor Corporation DS011641.prf www.fairchildsemi.com
74VHC4040
12-Stage Binary Counter
General Description
The VHC4040 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissipation. The VHC4040 is a 1 2-stage counter which increments on the negative edge of the input clock and all
outputs are reset to a low level by ap plying a logical high
on the reset input. An input protection circuit i nsures that
0V to 7V can be applied to the inputs wi thout r egard to the
supply voltage. This dev ice can be used to interf ace 5V to
3V systems and two supply systems such as battery
backup. Thi s ci r c ui t pr ev ent s d e vi ce d est r uc ti o n du e to m is matched supply and input voltages.
Features
■ High speed; f
MAX
= 210 MHz at VCC = 5V
■ Low power dissipation: I
CC
= 4 µA (max) at TA = 25°C
■ High noise immunity: V
NIH
=V
NIL
= 28% VCC (min)
■ Power down protection is provided on all inputs
■ Wide operating voltage range: V
CC
(opr) = 2V − 5.5V
■ Low noise: V
OLP
= 0.8V (max)
■ Pin and function compatible with 74HC4040
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code .
Connection Diagram Pin Descriptions
Order Number Package Number Package Description
74VHC4040M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74VHC4040MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC4040N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
Q
0–Q11
Flip-Flop Outputs
CP
Negative Edged Triggered Clock
MR Master Reset
www.fairchildsemi.com 2
74VHC4040
Logic Symbols
IEEE/IEC
Logic Diagram
Timing Diagram
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74VHC4040
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are valu es beyond whic h the device
may be damaged or ha ve its useful life impaire d. The datab ook specifications should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and o utput/input loading variables. Fairchild does not recommend operation outside databook specifications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float
DC Electrical Characteristics
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Voltage (V
IN
) −0.5V to +7.0V
DC Output Voltage (V
OUT
) −0.5V to VCC + 0.5V
Input Diode Current (I
IK
) −20 mA
Output Diode Current (I
OK
) ±20 mA
DC Output Current (I
OUT
) ±25 mA
DC V
CC
/GND Current (ICC) ±75 mA
Storage Temperature (T
STG
) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260°C
Supply Voltage (V
CC
)2.0V to +5.5V
Input Voltage (V
IN
)0V to +5.5V
Output Voltage (V
OUT
)0V to V
CC
Operating Temperature (T
OPR
) −40°C to +85°C
Input Rise and Fall Time (t
r
, tf)
V
CC
= 3.3V ± 0.3V 0 ∼ 100 ns/V
V
CC
= 5.0V ± 0.5V 0 ∼ 20 ns/V
Symbol Parameter
V
CC
(V)
TA = 25°CT
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
V
IH
HIGH Level Input 2.0 1.50 1.50
V
Voltage 3.0 − 5.5 0.7 V
CC
0.7 V
CC
V
IL
LOW Level Input 2.0 0.50 0.50
V
Voltage 3.0 − 5.5 0.3 V
CC
0.3 V
CC
V
OH
HIGH Level Output 2.0 1.9 2.0 1.9
V
VIN = V
IH
or V
IL
IOH = −50 µA
Voltage 3.0 2.9 3.0 2.9
4.5 4.4 4.5 4.4
3.0 2.58 2.48 IOH = −4 mA
4.5 3.94 3.80 IOH = −8 mA
V
OL
LOW Level Output 2.0 0.0 0.1 0.1
V
VIN = V
IH
or V
IL
IOL = 50 µA
Voltage 3.0 0.0 0.1 0.1
4.5 0.0 0.1 0.1
3.0 0.36 0.44 IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
I
IN
Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAVIN = 5.5V or GND
I
CC
Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND
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