Fairchild Semiconductor 74VHC373MX, 74VHC373MTCX, 74VHC373MTC, 74VHC373MSCX, 74VHC373M Datasheet
...
February 1993
Revised April 1999
74VHC373 Octal D-Type Latch with 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011555.prf www.fairchildsemi.com
74VHC373
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHC373 is an advanced high speed CMO S octal Dtype latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type
latch is controlled by a latc h enable input (LE) an d an output enable input (O E
). The latches appe ar transparent to
data when latch enable (LE) is HIGH. When LE is LOW, the
data that meets the setup ti me is LATCHED. When th e OE
input is HIGH, the eight outputs are in a high im pedance
state.
An input protection circuit en sures that 0V to 7V can be
applied to the input pins without re gard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as ba ttery back up . This circuit prevents device destruction due to m i sma tche d s upp l y
and input voltages.
Features
■ High Speed: tPD = 5.0 ns (typ) @ VCC = 5V
■ High Noise Immunity: V
NIH
= V
NIL
= 28% VCC (Min)
■ Power Down Protection is provided on all inputs
■ Low Noise: V
OLP
= 0.6V (typ)
■ Low Power Dissipation: I
CC
= 4 µA (Max) @ TA = 25°C
■ Pin and Function Compatible with 74HC373
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code .
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC373M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74VHC373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0–D7
Data Inputs
LE Latch Enable Input
OE
Output Enable Input
O
0–O7
3-STATE Outputs
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74VHC373
Functional Description
The VHC373 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch o utput will
change state each time its D input cha nges. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlle d
by the Output Enable (OE
) input. When OE is LOW, the
standard outputs are in the 2-state mode. When OE
is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Tr uth Table
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and shou ld not be used to estimate propagation delays.
Inputs Outputs
LE OE
D
n
O
n
XHX Z
HLL L
HLH H
LLX O
0
3 www.fairchildsemi.com
74VHC373
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are valu es beyond whic h the device
may be damaged or ha ve its useful life impaire d. The datab ook specifications should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and o utput/input loading variables. Fairchild does not recommend operation outside databook specifications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Parameter gu aranteed by design.
Supply Voltage (VCC) −0.5V to + 7.0V
DC Input Voltage (V
IN
) −0.5V to + 7.0V
DC Output Voltage (V
OUT
) −0.5V to VCC + 0.5V
Input Diode Current (I
IK
) −20 mA
Output Diode Current ±20 mA
DC Output Current (I
OUT
) ±25 mA
DC V
CC
/GND Current (ICC) ±75 mA
Storage Temperature (T
STG
) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260°C
Supply Voltage (V
CC
) 2.0V to + 5.5V
Input Voltage (V
IN
)0V to + 5.5V
Output Voltage (V
OUT
)0V to V
CC
Operating Temperature (T
OPR
) −40°C to +85°C
Input Rise and Fall Time (t
r
, tf)
V
CC
= 3.3V ± 0.3V 0 ∼ 100 ns/V
V
CC
= 5.0 ± 0.5V 0 ∼ 20 ns/V
Symbol Parameter
V
CC
(V)
TA = +25°CT
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
V
IH
HIGH Level 2.0 1.50 1.50
V
Input Voltage 3.0 − 5.5 0.7 V
CC
0.7 V
CC
V
IL
LOW Level 2.0 0.50 0.50
V
Input Voltage 3.0 − 5.5 0.3 V
CC
0.3 V
CC
V
OH
HIGH Level 2.0 1.9 2.0 1.9 VIN = VIHIOH = −50 µA
Output Voltage 3.0 2.9 3.0 2.9 V or V
IL
4.5 4.4 4.5 4.4
3.0 2.58 2.48
V
IOH = −4 mA
4.5 3.94 3.80 IOH = −8 mA
V
OL
LOW Level 2.0 0.0 0.1 0.1 VIN = VIHIOL = 50 µA
Output Voltage 3.0 0.0 0.1 0.1 V or V
IL
4.5 0.0 0.1 0.1
3.0 0.36 0.44
V
IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
I
OZ
3-STATE Output 5.5 ±0.25 ±2.5 µAVIN = VIH or V
IL
Off-State Current V
OUT
= VCC or GND
I
IN
Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAVIN = 5.5 or GND
I
CC
Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND
Symbol Parameter
V
CC
(V)
TA = +25°C
Units Conditions
Typ Limits
V
OLP
(Note 3)
Quiet Output Maximum Dynamic V
OL
5.0 0.6 0.9 V CL = 50 pF
V
OLV
(Note 3)
Quiet Output Minimum Dynamic V
OL
5.0 −0.6 −0.9 V CL = 50 pF
V
IHD
(Note 3)
Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL = 50 pF
V
ILD
(Note 3)
Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL = 50 pF
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