Fairchild Semiconductor 74VHC273SJX, 74VHC273SJ, 74VHC273N, 74VHC273MX, 74VHC273MTCX Datasheet
...
April 1994
Revised April 1999
74VHC273 Octal D-Type Flip-Flop
© 1999 Fairchild Semiconductor Corporation DS011670.prf www.fairchildsemi.com
74VHC273
Octal D-Type Flip-Flop
General Description
The VHC273 is an advan ced high speed CMOS Octal Dtype flip-flop fabricated with silicon gate CMOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The register has a common buffered Clock (CP) which is
fully edge-triggered. The state of e ach D input, o ne setup
time before the LOW-to-HIGH clock transition, is transferred to the correspond i ng f lip -flo p’s Q outpu t. T he M ast er
Reset (MR
) input will clear all flip-flops simultaneously. All
outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR
input.
An input protection circuit insures that 0V to 7V can be
applied to the inp uts pi n s wi t hou t reg ard t o the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. Th is circuit prevents device destruction due to m isma tche d s upp l y
and input voltages.
Features
■ High Speed: f
MAX
= 165 MHz (typ) at VCC = 5V
■ Low power dissipation: I
CC
= 4 µA (max) at TA = 25°C
■ High noise immunity: V
NIH
= V
NIL
= 28% VCC (min)
■ Power down protection is provided on all inputs
■ Low noise: V
OLP
= 0.9V (max)
■ Pin and function compatible with 74HC273
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
D
0–D7
Data Inputs
MR
Master Reset
CP Clock Pulse Input
Q
0–Q7
Data Outputs
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74VHC273
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transitio n
Logic Diagram
Please note that this diagram is provided o nly f or t he understanding o f lo gic operations and shou ld not be used to estimate propagation delays.
Operating Mode Inputs Outputs
MR
CP D
n
Q
n
Reset (Clear) L X X L
Load ’1’ H
HH
Load ’0’ H
LL
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74VHC273
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are valu es beyond whic h the device
may be damaged or ha ve its useful life impaire d. The datab ook specifications should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and o utput/input loading variables. Fairchild does not recommend operation outside databook specifications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Parameter gu aranteed by design.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Voltage (V
IN
) −0.5V to +7.0V
DC Output Voltage (V
OUT
) −0.5V to VCC + 0.5V
Input Diode Current (I
IK
) −20 mA
Output Diode Current (I
OK
) ±20 mA
DC Output Current (I
OUT
) ±25 mA
DC V
CC
/GND Current (ICC) ±75 mA
Storage Temperature (T
STG
) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260°C
Supply Voltage (V
CC
)2.0V to +5.5V
Input Voltage (V
IN
)0V to +5.5V
Output Voltage (V
OUT
)0V to V
CC
Operating Temperature (T
OPR
) −40°C to +85°C
Input Rise and Fall Time (t
r
, tf)
V
CC
= 3.3V ± 0.3V 0 ns/V ∼ 100 ns/V
V
CC
= 5.0V ± 0.5V 0 ns/V ∼ 20 ns/V
Symbol Parameter
V
CC
(V)
TA = 25°CT
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
V
IH
HIGH Level Input 2.0 1.50 1.50
V
Voltage 3.0 − 5.5 0.7 V
CC
0.7 V
CC
V
IL
LOW Level Input 2.0 0.50 0.50
V
Voltage 3.0 − 5.5 0.3 V
CC
0.3 V
CC
V
OH
HIGH Level Output 2.0 1.9 2.0 1.9
V
VIN = VIHIOH = −50 µA
Voltage 3.0 2.9 3.0 2.9 or V
IL
4.5 4.4 4.5 4.4
3.0 2.58 2.48
V
IOH = −4 mA
4.5 3.94 3.80 IOH = −8 mA
V
OL
LOW Level Output 2.0 0.0 0.1 0.1
V
VIN = VIHIOL = 50 µA
Voltage 3.0 0.0 0.1 0.1 or V
IL
4.5 0.0 0.1 0.1
3.0 0.36 0.44
V
IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
I
IN
Input Leakage 0 − 5.5 ±0.1 ±1.0
µA
VIN = 5.5V or GND
Current
I
CC
Quiescent Supply 5.5 4.0 40.0
µA
VIN = VCC or GND
Current
Symbol Parameter
V
CC
(V)
TA = 25°C
Units Conditions
Typ Limits
V
OLP
Quiet Output Maximum Dynamic V
OL
5.0 0.6 0.9
V
CL = 50 pF
(Note 3)
V
OLV
Quiet Output Minimum Dynamic V
OL
5.0 −0.6 −0.9
V
CL = 50 pF
(Note 3)
V
IHD
Minimum HIGH Level Dynamic Input Voltage 5.0 3.5
V
CL = 50 pF
(Note 3)
V
ILD
Maximum LOW Level Dynamic Input Voltage 5.0 1.5
V
CL = 50 pF
(Note 3)
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