Fairchild Semiconductor 74VHC221AM, 74VHC221ACW, 74VHC221ASJX, 74VHC221ASJ, 74VHC221AN Datasheet

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April 1994 Revised May 1999

74VHC221A Dual Non-Retriggerable Monostable Multivibrator

General Description

The VHC221A is an advanced high speed CMOS Monostable Multivibrator fabricated with silicon gate CMOS technology. It achieves the high speed opera tion simil ar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Each multivibrator features both a negative, A, and a po sitive, B, transition triggered input, either of whi ch can be used as an inhibit in put. Also included is a clear inp ut that when taken LOW resets the one-shot. The VHC221A ca n be triggered on the positive transition of the cl ear while A is held LOW and B is held HIGH. The VHC221A is non-retriggerable, and therefo re cannot be retriggered until the outpu t pulse tim es out. The output pulse width is determined by the equation:

PW = (Rx)(C x); where PW is in seconds, R is in ohms, and C is in farads.

Limits for R

and Cx are:

External capacitor, C

: No limit

External resistors, R

: VCC= 2.0V, 5 kΩ min

> 3.0V, 1 kΩ min

An input protection circuit ensures that 0 to 7V can be applied to the inp ut pins with out regard to the sup ply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as ba ttery back up . This circuit prevents device destruction due to m isma tche d s upp l y and input voltages.

Features

■ High Speed: tPD = 8.1 ns (typ) at VCC = 5V

■ Low Power Dissipation: I

= 4 µA (Max) at TA= 25 °C

■ Active State: I

= 600 µA (Max) at TA = 25°C

■ High Noise Immunity: V

NIH

= V

NIL

= 28% VCC (min)

■ Power down protection is provided on all inputs

■ Pin and function compatible with 74HC221A

Ordering Code:

Surface mount pack ages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the or dering code.

Logic Symbol

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74VHC221AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74VHC221ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC221AMTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC221AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74VHC221A

Truth Table

H = HIGH Voltage Level = HIGH-to-LOW Transition L = LOW Voltage Level



= LOW-to-HIGH Transition

X: Don’t Care

Block Diagrams

Note A: Cx, Rx, Dx are external Capacitor, Resistor, and Diode, respectively. Note B: External clamping diode, Dx;

External capacitor is charged to V

level in the wait state, i.e . when no trigger is appl ied.

If the supply voltage is turne d off, Cx disc harges mainly th rough th e intern al (paras itic) diode . If Cx is su fficiently la rge and V

drops rapidly, there will be some possibility o f damag in g the IC throu gh in rus h cu rrent or latch- up . If the ca pac itance of the supp ly volt age fi lter is larg e enough and VCC drops slowly, the in rush current is automatically limite d and damage to the IC is av oided. The maximum valu e of forwar d current th rough th e parasitic diode is

±20 mA. In the case of a large Cx, the limit of fall time of the supply voltage is deter-

mined as follows:

≥ (VCC −0.7) Cx/20 mA

is the time between the supply voltage turn off and the supply voltage reaching 0.4 VCC)

In the event a system does not satisfy the above condition, an external clamping diode (Dx) is needed to protect the IC from rush current.

System Diagram

Inputs Outputs

Function

BCLRQQ





Output Enable X L H L H Inhibit H X H L H Inhibit L





Output Enable LH



Output Enable X X L L H Reset

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74VHC221A

Timing Chart

Functional Description

1. Stand-by State The external capac itor (Cx) is fully ch arged to V

the Stand-by State. That mean s, before trigger ing, the Q

and QN transistors which are con nected to the Rx/

Cx node are in the off state. Two comparators that relate to the timing of the output p ulse, and two r eference voltage supplies turn off. The total supply curre nt is only leakage current.

2. Trigger Operation Trigger operation is effective in any of the following

three cases. First, the co ndition where the A

input is LOW, and B input has a rising signal; second, where the B input is HIGH, and the A input has a falling signal; and third, where the A

input is LOW and the B input is

HIGH, and the CLR

input has a rising signal.

After a trigger becomes e ffective, compara tors C1 a nd C2 start operating, and Q

is turned on. The exter nal

capacitor discharges thro ugh Q

. The voltage level at

the Rx/Cx node drops. If the Rx/Cx voltage level falls to the internal reference voltage V

ref

L, the output of C1

becomes LOW. The flip-flop is then reset an d Q

turns

off. At that moment C1 stops bu t C2 cont inues opera ting.

After Q

turns off, the voltage at the Rx/Cx node starts

rising at a rate determined by the time constant of external capacitor Cx and resistor Rx.

Upon triggering, output Q becomes HIGH, following some delay time of t he interna l F/F and gates . It stays HIGH even if the voltage of Rx/Cx changes from falling to rising. When Rx/Cx reaches the internal reference voltage V

ref

H, the output of C2 becomes LOW, the out-

put Q goes LOW and C2 stops its operation. That means, after trigger ing, when the voltage level of the Rx/Cx node reaches V

ref

H, the IC returns to its MONOSTABLE stat e. With large values of Cx and Rx, and ignoring the dis-

charge time of the capacitor a nd internal dela ys of the IC, the width of the outp ut pulse, t

(OUT), is as follows: t

(OUT) = 1.0 Cx Rx

3. Reset Operation In normal operation, the CLR

input is held HIGH. If

CLR

is LOW, a trigger has no affect because the Q output is held LOW and the tri gger control F/F is reset. Also, Q

turns on and Cx is charged rapidly to VCC.

This means if CLR

is set LOW, the IC goes into a wait

state.

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