Fairchild Semiconductor 74VHC175SJX, 74VHC175SJ, 74VHC175MX, 74VHC175N, 74VHC175MTCX Datasheet
...
August 1993
Revised April 1999
74VHC175 Quad D-Type Flip-Flop
© 1999 Fairchild Semiconductor Corporation DS011637.prf www.fairchildsemi.com
74VHC175
Quad D-Type Flip-Flop
General Description
The VHC175 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissipation.
The VHC175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D inputs is stored during the LOW-to-HIGH clock transition.
Both true and comp lemented outputs o f each flip-flop a re
provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without re gard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. Th is circuit prevents device destruction due to m ismatched supply
and input voltages.
Features
■ High Speed: f
MAX
= 210 MHz (typ) at VCC = 5V
■ Low power dissipation: I
CC
= 4 µA (max) at TA = 25°C
■ High noise immunity: V
NIH
= V
NIL
= 28% VCC (min)
■ Power down protection is provided on all inputs
■ Low noise: V
OLP
= 0.8V (max)
■ Pin and function compatible with 74HC175
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code .
Connection Diagram Pin Descriptions
Logic Symbols
IEEE/IEC
Order Number Package Number Package Description
74VHC175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
D
0–D3
Data Inputs
CP Clock Pulse Input
MR
Master Reset Input
Q
0–Q3
True Outputs
Q
0
–Q
3
Complement Outputs
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74VHC175
Functional Description
The VHC175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q
outputs. The Clock
and Master Reset are common. The four flip-flops will store
the state of their indivi dual D inputs on the LOW-to- HIGH
clock (CP) transition, causing individual Q and Q
outputs to
follow. A LOW input on the Master Reset (MR
) will force all
Q outputs LOW and Q
outputs HIGH independ en t of Clock
or Data inputs. The VHC175 is useful for general logic
applications where a common Master Reset and Clock are
acceptable.
Tr uth Table
H = HIGH Voltage Level
L = LOW Voltage Level
t
n
= Bit Time before Clock Pulse
t
n+1
= Bit Time after Clock Pulse
Logic Diagram
Please note that this diagram is provided o nly f or t he understanding of logic operations and shou ld not be used to estimate pro pagation delays.
Inputs Outputs
@ t
n
, MR = H@ t
n+1
D
n
Q
n
Q
n
LLH
HHL
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74VHC175
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are valu es beyond whic h the device
may be damaged or ha ve its useful life impaire d. The datab ook specifications should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and o utput/input loading variables. Fairchild does not recommend operation outside databook specifications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Parameter gu aranteed by design.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Voltage (V
IN
) −0.5V to +7.0V
DC Output Voltage (V
OUT
) −0.5V to VCC + 0.5V
Input Diode Current (I
IK
) −20 mA
Output Diode Current (I
OK
) ±20 mA
DC Output Current (I
OUT
) ±25 mA
DC V
CC
/GND Current (ICC) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260°C
Supply Voltage (V
CC
)2.0V to +5.5V
Input Voltage (V
IN
)0V to +5.5V
Output Voltage (V
OUT
)0V to V
CC
Operating Temperature (T
OPR
) −40°C to +85°C
Input Rise and Fall Time (t
r
, tf)
V
CC
= 3.3V ± 0.3V 0 ∼ 100 ns/V
V
CC
= 5.0V ± 0.5V 0 ∼ 20 ns/V
Symbol Parameter
V
CC
(V)
TA = 25°CT
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
V
IH
HIGH Level Input 2.0 1.50 1.50
V
Voltage 3.0 − 5.5 0.7 V
CC
0.7 V
CC
V
IL
LOW Level Input 2.0 0.50 0.50
V
Voltage 3.0 − 5.5 0.3 V
CC
0.3 V
CC
V
OH
HIGH Level Output 2.0 1.9 2.0 1.9
V
VIN = VIHIOH = −50 µA
Voltage 3.0 2.9 3.0 2.9 or V
IL
4.5 4.4 4.5 4.4
3.0 2.58 2.48
V
IOH = −4 mA
4.5 3.94 3.80 IOH = −8 mA
V
OL
LOW Level Output 2.0 0.0 0.1 0.1
V
VIN = VIHIOL = 50 µA
Voltage 3.0 0.0 0.1 0.1 or V
IL
4.5 0.0 0.1 0.1
3.0 0.36 0.44
V
IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
I
IN
Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAVIN = 5.5V or GND
I
CC
Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND
Symbol Parameter
V
CC
(V)
TA = 25°C
Units Conditions
Typ Limits
V
OLP
(Note 3)
Quiet Output Maximum Dynamic V
OL
5.0 0.4 0.8 V CL = 50 pF
V
OLV
(Note 3)
Quiet Output Minimum Dynamic V
OL
5.0 −0.4 −0.8 V CL = 50 pF
V
IHD
(Note 3)
Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL = 50 pF
V
ILD
(Note 3)
Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL = 50 pF
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