Fairchild Semiconductor 74VHC161SJX, 74VHC161SJ, 74VHC161N, 74VHC161MX, 74VHC161MTCX Datasheet

August 1993
Revised April 1999

74VHC161 4-Bit Binary Counter with Asynchronous Clear

© 1999 Fairchild Semiconductor Corporation DS011635.prf www.fairchildsemi.com

74VHC161
4-Bit Binary Counter with Asynchronous Clear

General Description

The VHC161 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi­pation. The VHC161 is a hig h-sp ee d syn chronous modulo­16 binary counter. This device is synchronously presettable
for application in programmable dividers and have two
types of Count Enable input s plus a Terminal Count output
for versatility in forming synchronous multistage counters.
The VHC161 has an asynchronous Master Reset input that
overrides all other inputs and forces the outputs LOW. An
input protection circuit insures that 0V to 7V can be applied
to the input pins without regard to the su pply voltag e. This
device can be used to interfa ce 5V to 3V syste ms and two
supply systems such as b attery backup. This circuit pre-

vents device destruction due to mismatched supply and
input voltages.

Features

■ High Speed:
f

MAX

= 185 MHz (typ) at TA = 25°C

■ Synchronous counting and loading

■ High-speed synchronous expan sion

■ Low power dissipation:

I

CC

= 4 µA (max) at TA= 25°C

■ High noise immunity: V

NIH

= V

NIL

= 28% VCC (min)

■ Power down protection provided on all inputs

■ Low noise: V

OLP

= 0.8V (max)

■ Pin and function compatible with 74HC161

Ordering Code:

Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code .

Logic Symbols

IEEE/IEC

Order Number Package Number Package Description

74VHC161M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC161N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2

74VHC161

Connection Diagram Pin Descriptions

Functional Description

The VHC161 counts i n modulo-16 bi nary sequenc e. From
state 15 (HHHH) it increments to state 0 (LLLL). The clock
inputs of all flip-flops a re driven in para llel through a clock
buffer. Thus all changes of the Q outputs (except due to
Master Reset of the VHC161) occur as a result of, and syn­chronous with, the LOW-to-HIGH transition o f the CP input
signal. The circuits have four fundamental modes of opera­tion, in order of prece dence: asynchronous reset, parallel

load, count-up and hold. Five control inputs—Master
Reset, Parallel Enable (PE

), Count Enable Parallel (CEP)
and Count Enabl e Trickle (CET)—determine the mode of
operation, as show n in the Mode Select Table. A LOW sig­nal on MR

overrides all other inputs an d asynchronously

forces all outputs LOW. A LOW signal on PE

overrides

counting and allows information on the Parallel Data (P

n

)

inputs to be loaded into the flip-flops on the next rising
edge of CP. With PE

and MR HIGH, CEP and CET permit
counting when both are HIGH. Conversely, a LOW signal
on either CEP or CET inhibits counting.

The VHC161 uses D-type edge-triggered flip-flops and
changing the PE

, CEP and CET inputs when the CP is in
either state does not cause errors, provided that the recom­mended setup and hold times, with respect to the rising
edge of CP, are observed.

The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement sync hro-

nous multistage counters, the TC outputs can be used with
the CEP and CET inputs in two differ ent ways.

Figure 1

shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup time
sets the upper limit o n clock frequency. For faster clock
rates, the carry lookahead connecti ons shown in

Figure 2

are recommended. In this sch eme the ripple del ay through
the intermediate stages commences with the same clock
that causes the first stage to tick over from m ax to min in
the Up mode, or m in to m ax in th e Dow n mo de, to start its
final cycle. Since this final cycle require s 16 clocks to co m­plete, there is plenty of time for the ripple to progress
through the intermediate stages. The critical timing that lim­its the clock period is th e CP to TC d elay of the fir st stage
plus the CEP to CP setup time of the last stage. T he TC
output is subject t o decoding spikes due to intern al race
conditions and is th erefore not recommen ded for u se as a
clock or asynchronous reset for flip-flops, registers or
counters.

Logic Equations: Count Enable = CEP • CET • PE

TC = Q0 • Q1 • Q2 • Q3 • CET

FIGURE 1. Multistage Counter with Ripple Carry

FIGURE 2. Multistage Counter with Lookahead Carry

Pin Names Description

CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock Pulse Input
MR

Asynchronous Master Reset Input

P

0–P3

Parallel Data Inputs

PE

Parallel Enable Inputs

Q

0–Q3

Flip-Flop Outputs

TC Terminal Count Output

3 www.fairchildsemi.com

74VHC161

Mode Select Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

State Diagram

Block Diagram

Please note that this d iagram is provided only f or t he understanding of logic operations and shou ld not be used to estimat e propagation delays.

MR PE CET CEP

Action on the Rising

Clock Edge (



)

L X X X Reset (Clear)
H L X X Load (P

n→Qn

)
HHHHCount (Increment)
H H L X No Change (Hold)
H H X L No Change (Hold)