Fairchild Semiconductor 74VHC157N, 74VHC157MX, 74VHC157MTCX, 74VHC157MTC, 74VHC157MSCX Datasheet
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November 1992
Revised April 1999
74VHC157 Quad 2-Input Multiplexer
© 1999 Fairchild Semiconductor Corporation DS011536.prf www.fairchildsemi.com
74VHC157
Quad 2-Input Multiplexer
General Description
The VHC157 is an adva nced high speed CMOS Quad 2Channel Multiplexer fabricated with silicon gate CMOS
technology. It achieves the high speed opera tion simil ar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
It consists of four 2-input digita l multiplexers with co mmon
select and enable inpu ts. When the ENAB LE
input is held
“H” level, selection of data is inhibited and all the outputs
become “L” level. The SELECT decoding determines
whether the I
0x
or I1x inputs get routed t o th eir cor resp on ding outputs.
An Input protection cir cuit ensures that 0V to 7V can be
applied to the input pins without re gard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and on two supply systems such as batter y back up. This
circuit prevents device destruction due to mismatched supply and input voltages.
Features
■ High Speed: tPD = 4.1 ns (typ) at VCC = 5V
■ Low power dissipation: I
CC
= 4 µA (max.) at TA = 25°C
■ High noise immunity: V
NIH
= V
NIL
= 28% VCC (min.)
■ Power down protection is provided on all inputs
■ Low noise: V
OLP
= 0.8V (max.)
■ Pin and function compatible with 74HC157
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC157M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74VHC157SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC157MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC157N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
I
0a–I0d
Source 0 Data Inputs
I
1a–I1d
Source 1 Data Inputs
E
Enable Input
S Select Input
Z
a–Zd
Outputs
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74VHC157
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Functional Description
The VHC157 is a quad 2-input multiplexer. It selects four
bits of data from two sources u nder the cont rol of a common Select input (S). Th e Enable input (E
) is active-LOW.
When E
is HIGH, all of the outputs (Z) are forced LOW
regardless of all other inputs. The VHC157 is the logic
implementation of a 4-pole, 2-position switch where the
position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs
are shown below:
Z
a
= E • (I1a • S + I0a • S)
Z
b
= E • (I1b • S + I0b • S)
Z
c
= E • (I1c • S + I0c • S)
Z
d
= E • (I1d • S + I0d • S)
A common use of the VH C157 is the mo ving of dat a from
two groups of registers to four common output busses. The
particular register from which the data comes is determined
by the state of t he S elect in put . A less ob vious us e is as a
function generator. The VHC 157 can genera te any four of
the sixteen different functions of two variables with one
variable common. This is useful for implementing gating
functions.
Logic Diagram
Please note that this diagram is provided only f or t he understanding of lo gic operations and should not be used to estimate propagation delays.
Inputs Outputs
E
SI0I
1
Z
HX X X L
LH X L L
LH X H H
LL L X L
LL H X H
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74VHC157
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are valu es beyond whic h the device
may be damaged or ha ve its useful life impaire d. The datab ook specifications should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and o utput/input loading variables. Fairchild does not recommend operation outside databook specifications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Parameter gu aranteed by design.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Voltage (V
IN
) −0.5V to +7.0V
DC Output Voltage (V
OUT
) −0.5V to VCC + 0.5V
Input Diode Current (I
IK
) −20 mA
Output Diode Current (I
OK
) ±20 mA
DC Output Current (I
OUT
) ±25 mA
DC V
CC
/GND Current (ICC) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seco nds) 260°C
Supply Voltage (V
CC
)2.0V to +5.5V
Input Voltage (V
IN
)0V to +5.5V
Output Voltage (V
OUT
)0V to V
CC
Operating Temperature (T
OPR
) −40°C to +85°C
Input Rise and Fall Time (t
r
, tf)
V
CC
= 3.3V ± 0.3V 0 ∼ 100 ns/V
V
CC
= 5.0V ± 0.5V 0 ∼ 20 ns/V
Symbol Parameter
V
CC
(V)
TA = 25°CT
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
V
IH
HIGH Level 2.0 1.50 1.50
V
Input Voltage 3.0 − 5.5 0.7 V
CC
0.7 V
CC
V
IL
LOW Level 2.0 0.50 0.50
V
Input Voltage 3.0 − 5.5 0.3 V
CC
0.3 V
CC
V
OH
HIGH Level 2.0 1.9 2.0 1.9 VIN = VIHIOH = −50 µA
Output Voltage 3.0 2.9 3.0 2.9 V or V
IL
4.5 4.4 4.5 4.4
3.0 2.58 2.48
V
IOH = −4 mA
4.5 3.94 3.80 IOH = −8 mA
V
OL
LOW Level 2.0 0.0 0.1 0.1 VIN = VIHIOL = 50 µA
Output Voltage 3.0 0.0 0.1 0.1 V or V
IL
4.5 0.0 0.1 0.1
3.0 0.36 0.44
V
IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
I
IN
Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAVIN = 5.5V or GND
I
CC
Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND
Symbol Parameter
V
CC
(V)
TA = 25°C
Units Conditions
Typ Limits
V
OLP
Quiet Output Maximum 5.0 0.3 0.8 V CL = 50 pF
(Note 3) Dynamic V
OL
V
OLV
Quiet Output Minimum 5.0 −0.3 −0.8 V CL = 50 pF
(Note 3) Dynamic V
OL
V
IHD
Minimum HIGH Level 5.0 3.5 V CL = 50 pF
(Note 3) Dynamic Input Voltage
V
ILD
Maximum LOW Level 5.0 1.5 V CL = 50 pF
(Note 3) Dynamic Input Voltage
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