August 1993
Revised April 1999
74VHC153 Dual 4-Input Multiplexer
© 1999 Fairchild Semiconductor Corporation DS011634.prf www.fairchildsemi.com
74VHC153
Dual 4-Input Multiplexer
General Description
The VHC153 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissipation. The VHC153 i s a high-speed Dual 4-Input Multiplexer with common select inputs and individual enable
inputs for each section. It can select two lines of d ata fro m
four sources. The t wo buffered outpu ts pre sen t data in t he
true (non-inverted) form. In addition to multipl exer operation, the VHC153 can act as a function generator a nd generate any two functions of three variables. An input
protection circuit insure s that 0V to 7V can be applied to
the input pins without regard to the suppl y voltage. This
device can be used to in terface 5V to 3V sys tems an d two
supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and
input voltages.
Features
■ High Speed: tPD = 5.0 ns at TA = 25°C
■ Low power dissipation: I
CC
= 4 µA (max) at TA = 25°C
■ High noise immunity: V
NIH
= V
NIL
= 28% VCC (min)
■ Power down protection is provided on all inputs
■ Pin and function compatible with 74HC153
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code .
Logic Symbols
IEEC/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC153M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC153SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC153MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC153N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
I
0a–I3a
Side A Data Inputs
I
0b–I3b
Side B Data Inputs
S
0
, S
1
Common Select Inputs
E
a
Side A Enable Input
E
b
Side B Enable Input
Z
a
Side A Output
Z
b
Side B Output