November 1992
Revised April 1999
74VHC138 3-to-8 Decoder/Demultiplexer
© 1999 Fairchild Semiconductor Corporation DS011537.prf www.fairchildsemi.com
74VHC138
3-to-8 Decoder/Demultiplexer
General Description
The VHC138 is an advanced high speed CMOS 3-to-8
decoder/demultiplexer fabricated with silicon gate CMOS
technology. It achieves the high speed opera tion simil ar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
When the device is enabled, 3 bina ry select inpu ts (A
0
, A
1
and A2) determine which one of the outputs (O0–O7) will go
LOW. When enable input E
3
is held LOW or either E1 or E
2
is held HIGH, decoding function is inhib ited and all outputs
go HIGH. E
3
, E1 and E2 inputs are provided to ease cas-
cade connection and for use as an address decoder f or
memory systems. An input protection cir cuit ensures that
0V to 7V can be applied to the inpu t pins without re gard to
the supply voltage. This device can be used to interface 5V
to 3V systems and two supply systems such as battery
back up. This circuit prevents device destruction due to
mismatched supply and input voltages.
Features
■ High Speed: tPD = 5.7ns (typ) at TA = 25°C
■ Low power dissipation: I
CC
= 4 µA (max.) at TA = 25°C
■ High noise immunity: V
NIH
= V
NIL
= 28% VCC (min.)
■ Power down protection provided on all inputs
■ Pin and function compatible with 74HC138
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74VHC138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74VHC138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC138MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC138N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
A
0–A2
Address Inputs
E
1–E2
Enable Inputs
E
3
Enable Input
O
0–O7
Outputs