Fairchild Semiconductor 74VHC132SJX, 74VHC132SJ, 74VHC132N, 74VHC132MX, 74VHC132MTCX Datasheet
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September 1995
Revised April 1999
74VHC132 Quad 2-Input NAND Schmitt Trigger
© 1999 Fairchild Semiconductor Corporation DS012124.prf www.fairchildsemi.com
74VHC132
Quad 2-Input NAND Schmitt Trigger
General Description
The VHC132 is an advance d high speed CMOS 2-input
NAND Schmitt Trigger Gate fabricated with silicon gate
CMOS technology. It achieves the high-speed operation
similar to Bipolar Schottky TTL while maintaining the
CMOS low power dissi pation. Pin configuration and function are th e s am e as t h e V HC 0 0 bu t t he in pu t s ha ve hy s ter esis between the positive-go ing and negative-going input
thresholds, which are capable of transforming slowly
changing input signals in to sharply defined, jitte r-free output signals. Thus greater n oise margin then conventional
gates is provided. An input protection circuit ensures th at
0V to 7V can be applied to th e input p ins with out reg ard to
the supply voltage. This device can be used to interface 5V
to 3V systems and two supply systems such as battery
backup. Thi s ci r c ui t pr ev ent s d e vi ce d est r uc ti o n du e to m is matched supply and input voltages.
Features
■ High Speed: tPD = 3.9 ns (typ) at VCC = 5 V
■ Power down protection is provided on all inputs
■ Low power dissipation: I
CC
= 2 µA (max) at TA = 25°C
■ Low noise: V
OLP
= 0.8 V (max)
■ Pin and function compatible with 74HC132
Ordering Code:
Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code.
Connection Diagram
Pin Descriptions
Logic Diagram
Truth Table
Order Number Package Number Package Description
74VHC132M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74VHC132SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC132MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC132N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
A
n
, B
n
Inputs
Y
n
Outputs
ABY
LLH
LHH
HLH
HHL
www.fairchildsemi.com 2
74VHC132
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or ha ve its useful li fe impaire d. The datab ook specifications should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and ou tput/input loading variables. Fairchild does not recom mend operation outside databook specifications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Voltage (V
IN
) −0.5V to +7.0V
DC Output Voltage (V
OUT
) −0.5V to VCC + 0.5V
Input Diode Current (I
IK
) −20 mA
Output Diode Current (I
OK
) ±20 mA
DC Output Current (I
OUT
) ±25 mA
DC V
CC
/GND Current (ICC) ±50 mA
Storage Temperature ( T
STG
) −65°C to +150°C
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260°C
Supply Voltage (V
CC
) 2.0V to +5.5V
Input Voltage (V
IN
)0V to +5.5V
Output Voltage (V
OUT
) 0V to V
CC
Operating Temperature (T
OPR
) −40°C to +85°C
Symbol Parameter
V
CC
(V)
TA = 25°CT
A
= −40°C to +85°C
Units Conditions
Min Typ Max Min Max
V
P
Positive 3.0 2.20 2.20
VThreshold Voltage 4.5 3.15 3.15
5.5 3.85 3.85
V
N
Negative 3.0 0.90 0.90
VThreshold Voltage 4.5 1.35 1.35
5.5 1.65 1.65
V
H
Hysteresis 3.0 0.30 1.20 0.30 1.20
VOutput Voltage 4.5 0.40 1.40 0.40 1.40
5.5 0.50 1.60 0.50 1.60
V
OH
HIGH Level 2.0 1.9 2.0 1.9 VIN = VIHIOH = −50 µA
Output Voltage 3.0 2.9 3.0 2.9 V or V
IL
4.5 4.4 4.5 4.4
3.0 2.58 2.48 V IOH = −4 mA
4.5 3.94 3.80 IOH = −8 mA
V
OL
LOW Level 2.0 0.0 0.1 0.1 VIN = VIHIOL = 50 µA
Output Voltage 3.0 0.0 0.1 0.1 V or V
IL
4.5 0.0 0.1 0.1
3.0 0.36 0.44 V IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
I
IN
Input Leakage Current 0–5.5 ±0.1 ±1.0 µAVIN = 5.5V or GND
I
CC
Quiescent Supply Current 5.5 2.0 20.0 µAVIN = VCC or GND
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