Fairchild Semiconductor 74VCX32500 Datasheet
March 2001
Revised August 2003
74VCX32500
Low Voltage 36-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
74VCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 3.6V Toler ant Inputs and Outputs
General Description
The VCX32500 is an 36-bit universal bus transceiver which
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each dir ection is controlled by output-enable
(OEAB and OEBA
clock (CLKAB
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB
active. When OEAB is LOW, the outputs are in a highimpedance state.
Data flow for B to A is similar to tha t of A to B but uses
, LEBA, and CLKBA. The output enables are com-
OEBA
plementary (OEAB is active HIGH and OEBA
LOW).
The VCX32500 is designe d for low voltage (1.4V to 3.6V)
applications with I/O capability up to 3.6V.
V
CC
The 74VCX32500 i s fabricated with an advanc ed CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
), latch-enable (LEAB and LEBA), and
and CLKBA) inputs. For A-to-B data flow, the
. When OEAB is HIGH, the outputs are
is active
Features
■ 1.4V to 3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
(A to B, B to A)
■ t
PD
2.9 ns max for 3.0V to 3.6V V
■ Power-down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ Static Drive (I
±24 mA @ 3.0V V
■ Uses patented noise/EMI reductio n circuitr y
■ Latchup performance exceeds 300 mA
■ ESD performance:
Human body model
Machine model
■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state d uring power up or power
down, OEBA
should be tied to GND through a pull-down resist ors; the minimum v alue of
the resistor is determined by the current -s ourcing capability of t he driver.
should be tied to VCC through a pull-up res istor and OEAB
OH/IOL
)
CC
>200V
Ordering Code:
Order Number Package Number Package Description
74VCX32500G
(Note 2)(Note 3)
Note 2: Ordering Code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
BGA114A 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
CC
> 2000V
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Connection Diagram
74VCX32500
(Top Thru View)
FBGA Pin Assignments
123 4 5 6
A 1A
B 1A41A3OEAB1GND 1B31B
C 1A61A5GND GND 1B51B
D 1A81A7V
E 1A101A9GND GND 1B91B
F 1A121A11GND GND 1B111B
G 1A141A13V
H 1A151A16GND GND 1B161B
J 1A171A18OEBA1CLKBA11B181B
K NC LEAB2LEBA1GND CLKAB2NC
L 2A
M 2A42A3GND GND 2B32B
N 2A62A5V
P 2A82A7GND GND 2B72B
R 2A102A9GND GND 2B92B
T 2A122A11V
U 2A142A13GND GND 2B132B
V 2A152A16OEBA2CLKBA22B162B
W 2A172A18LEBA2GND 2B182B
1A1LEAB1CLKAB11B11B
2
V
CC
CC
V
CC
CC
2A1OEAB2GND 2B12B
2
V
CC
CC
V
CC
CC
1B71B
1B131B
2B52B
2B112B
2
4
6
8
10
12
14
15
17
2
4
6
8
10
12
14
15
17
Pin Descriptions
Pin Names Description
OEAB
n
OEBA
n
, LEBAnLatch Enable Inputs
LEAB
n
CLKAB
CLKBA
1A
–1A
1
2A1–2A
–1B
1B
1
2B1–2B
Output Enable Input for A to B Direction
(Active HIGH)
Output Enable Input for B to A Direction
(Active LOW)
,
Clock Inputs
n
n
Side A Inputs or 3-STATE Outputs
18
18
Side B Inputs or 3-STATE Outputs
18
18
Function Table
(Note 4)
Inputs Outputs
OEAB
LEABnCLKABnA
n
n
B
n
LXXX Z
HHX L L
HHX H H
HL
HL
HLHXB
HL LXB
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Note 4: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA
LEBA and CLKBA
Note 5: Output level be fore the indicated steady-s tate input conditions
were established.
Note 6: Output level be fore the indicated steady-s tate input conditions
were established, provided that CLKA B
. OEBA is active LOW.
↓ LL
↓ HH
(Note 5)
0
(Note 6)
0
was LOW before LEAB went LOW.
,
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Logic Diagrams
74VCX32500
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