Fairchild Semiconductor 74VCX32374 Datasheet
74VCX32374
Low Voltage 32-Bit D-Type Flip-Flops
with 3.6V Tolerant Inputs and Outputs
74VCX32374 Low Voltage 32-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
December 2000
Revised November 2002
General Description
The VCX32374 contains thirty-two non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus oriented applications. The dev ice is byte controlled. A buffered clock (CP) and ou tput enable (OE
each byte and can be shorted together for full 32-bit operation.
The 74VCX32374 is designed for low voltage (1.2V to
3.6V) V
The 74VCX32374 i s fabricated with an advanc ed CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
applications with I/O compatibility up to 3.6V.
CC
) are common to
Features
■ 1.2V to 3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
■ t
PD
3.0 ns max for 3.0V to 3.6V V
■ Power-off high impedance inputs and outputs
■ Supports live insertion and withdrawal (Note 1)
■ Static Drive (I
±24 mA @ 3.0V V
■ Uses patented noise/EMI reductio n circuitr y
■ Latch-up performance exce eds 300 mA
■ ESD performance:
Human body model
Machine model
■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state d uring power up or power
should be tied to VCC through a pull-up r esistor; the min imum
down, OE
value of the res istor is d eter mine d by the cu rre nt-sou rcin g ca pa bility of t he
driver.
OH/IOL
)
CC
> 200V
Ordering Code:
Order Number Package Number Package Descriptions
74VCX32374G
(Note 2)(Note 3)
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
BGA96A 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Logic Symbol
CC
> 2000V
© 2002 Fairchild Semiconductor Corporation DS500402 www.fairchildsemi.com
Connection Diagram
74VCX32374
(Top Thru View)
Pin Descriptions
Pin Names Description
OE
CP
I
0–I31
O
0–O31
n
n
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
Outputs
FBGA Pin Assignments
123456
A O
B O3O2GND GND I
C O5O4V
D O7O6GND GND I
E O9O8GND GND I
F O11O10V
G O13O12GND GND I
H O14O15OE2CP2I
J O
K O19O18GND GND I
L O21O20V
M O23O22GND GND I
N O25O24GND GND I
P O27O26V
R O29O28GND GND I
T O30O31OE4CP4I
O0OE1CP1I
1
CCVCCI4
CCVCCI10I11
17O16
OE3CP3I
CCVCCI20I21
CCVCCI26I27
0
2
6
8
12I13
15I14
16I17
18I19
22I23
24I25
28I29
31I30
I
1
I
3
I
5
I
7
I
9
Truth Tables
Inputs Outputs Inputs Outputs
CP
LLXO
XHXZ XHXZ
CP
LLXO
XHXZ XHXZ
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
= Previous O0 before HIGH-to-LOW of CP
O
0
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OE
1
I0–I
1
O0–O
7
7
LHH
LLL
0
Inputs Outputs Inputs Outputs
OE
3
I16–I23O16–O
3
23
LHH
LLL
0
CP
LLXO
CP
LLXO
OE
2
I8–I
2
15O8–O15
LHH
LLL
0
OE
4
4I24–I31O24–O31
LHH
LLL
0
Functional Description
The 74VCX32374 consists of thirty-two edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device i s byte contr olled wit h each byte func tioning identically, but independent of the other. The control
pins can be shorted to gether to obtain f ull 3 2-b it o per ati o n.
Each clock has a buffered clock and buffered Output
Enable common to all flip-flops within that byte. The
description which follows applies to each byte. Each
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
flip-flop will store the state of their individual I inputs that
meet the setup and hold time requirements on the
LOW-to-HIGH Clock (CP
Enable (OE
able at the outputs. Wh en OE
the high impedance state. Operations of the OE
does not affect the state of the flip-flops.
) LOW, the contents of the flip-flops are avail-
n
) transition. With the Output
n
is HIGH, the outputs go to
n
input
n
74VCX32374
Byte 3 (16:23)
Byte 4 (24:31)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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