Fairchild Semiconductor 74VCX16500MTDX, 74VCX16500MTD Datasheet
March 1998
Revised April 1999
74VCX16500 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
© 1999 Fairchild Semiconductor Corporation DS500089.prf www.fairchildsemi.com
74VCX16500
Low Voltage 18-Bit Universal Bus Transceivers with
3.6V Tolerant Inputs and Outputs
General Description
The VCX16500 is an 18-bit universal bus transceiver which
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each dir ection is controlled by o utput-enable
(OEAB and OEBA
), latch-enable (LEAB and LEBA), and
clock (CLKAB
and CLKBA) inputs. For A-to-B data flow, the
device operates in the t ransparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB
. When OEAB is HIGH, the outputs are
active. When OEAB is LOW, the outputs are in a highimpedance state.
Data flow for B to A is similar to tha t of A to B but uses
OEBA
, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA
is active
LOW).
The VCX16500 is de sign ed for low voltage (1.65V to 3.6V)
V
CC
applications with I/O capability up to 3.6V.
The 74VCX16500 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
■ 1.65V–3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
■ t
PD
(A to B, B to A)
2.9 ns max for 3.0V to 3.6V V
CC
3.5 ns max for 2.3V to 2.7V V
CC
7.0 ns max for 1.65V to 1.95V V
CC
■ Power-down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ Static Drive (I
OH/IOL
)
±24 mA @ 3.0V V
CC
±18 mA @ 2.3V V
CC
±6 mA @ 1.65V V
CC
■ Uses patented noise/EMI reduction circuitry
■ Latchup performance exceeds 300 mA
■ ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state d uring power up or power
down, OEBA
should be tied to VCC through a pull-up res istor and OEAB
should be tied to GND through a pull-down resistors; the minimum value of
the resistor is determined by the current-s ourcing capability of the driver.
Ordering Code:
Devices also availab le on Tape and Reel. Specify by appendin g t he s uffix letter “X” to the orderin g c ode.
Order Number Package Number Package Description
74VCX16500MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
www.fairchildsemi.com 2
74VCX16500
Connection Diagram Pin Descriptions
Function Table
(Note 2)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Note 2: A-to-B data flow is shown; B-to-A flow is si milar but uses OE BA
,
LEBA and CLKBA
. OEBA is active LOW.
Note 3: Output level before the indicated steady-state inp ut conditions
were established.
Note 4: Output level before the indicated steady-state inp ut conditions
were established, provided that CLKAB
was LOW before LE AB went LOW.
Pin Names Description
OEAB Output Enable Input for A to B Direction
(Active HIGH)
OEBA
Output Enable Input for B to A Direction
(Active LOW)
LEAB, LEBA Latch Enable Inputs
CLKAB
,
CLKBA
Clock Inputs
A
1–A18
Side A Inputs or 3-STATE Outputs
B
1–B18
Side B Inputs or 3-STATE Outputs
Inputs Outputs
OEAB LEAB CLKAB
A
n
B
n
LXXX Z
HHXL L
HHXH H
HL↓ LL
HL↓ HH
HLHXB
0
(Note 3)
HLLXB
0
(Note 4)
3 www.fairchildsemi.com
74VCX16500
Logic Diagram
Loading...