Fairchild Semiconductor 74VCX164245MTDX, 74VCX164245MTD Datasheet
© 2000 Fairchild Semiconductor Corporation DS500159 www.fairchildsemi.com
March 2000
Revised March 2000
74VCX164245 Low Voltage 16-Bit Dual Supply T ranslating Transceiver with 3-STATE Outputs
74VCX164245
Low Voltage 16-Bit Dual Supply Translating Transceiver
with 3-STATE Outputs
General Description
The VCX164245 is a dual supp ly, 16-bit translating transceiver that is designed for 2 way asynchr onous communication between busses at different supply voltages by
providing true signal tr ans lati on . T he sup ply r ail s co nsis t of
V
CCB
, which is the higher potential rail operating at 2.3 to
3.6V and V
CCA
, which is the lower potential rail operating at
1.65 to 2.7V. (V
CCA
must be less than or equal to V
CCB
for
proper device operati on.) This dual supply design allows
for translation from 1.8V to 2.5V busses to busses at a
higher potential, up to 3.3V.
The Transmit/Receive (T/R
) input determines the direct ion
of data flow. Transmit (active-HIGH) enables data from A
Ports to B Ports; Recei ve (active- LOW) en ables data from
B Ports to A Ports.The Output Enable (OE
) input, when
HIGH, disables both A and P Ports by placing them in a
High-Z condition. The A Port interfaces with the lower voltage bus (1.8 − 2.5V); The B Port i nterfa ces with th e higher
voltage bus (2.7 − 3.3V). Also the V CX16 4245 is de sign ed
so that the control pins (T/R
n
, OEn) are supplied by V
CCB
.
The 74VCX164245 is suit able for mixed voltage applications such as notebook compute rs using a 1.8V CPU and
3.3V peripheral components. It is fabricated with an
Advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
■ Bidirectional interface between busses ranging from
1.65V to 3.6V
■ Supports Live Insertion and Withdrawal (Note 1)
■ Static Drive (I
OH/IOL
)
±24 mA @ 3.0V V
CC
±18 mA @ 2.3V V
CC
±6 mA @ 1.65V V
CC
■ Uses patented noise/EMI reduction circuitry
■ Functionally compatible with 74 series 16245
■ Latchup performance exceeds 300 mA
■ ESD performance:
Human Body Model >2000V
Machine model >200V
Note 1: To ensure the h igh impedance state during power up or power
down, OE
n
should be tie d t o V
CCB
through a pull up resistor. The minimum
value of the res istor is dete rmin ed by the curr ent sou rcing ca pabilit y o f the
driver.
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Logic Diagram Pin Descriptions
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74VCX164245MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
T/R
n
Transmit/Receive Input
A
0–A15
Side A Inputs or 3-STATE Outputs
B
0–B15
Side B Inputs or 3-STATE Outputs
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74VCX164245
Connection Diagram Tr uth Tables
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Translator Power Up Sequence Recommendations
To guard against power up problems, some simple guidelines need to b e adhered t o. The VCX16 4245 is de signed
so that the control pins (T/R
n, OEn) are supplied by V
CCB
.
Therefore the first recommendation is to begin by powering
up the control side of the device, V
CCB
. The OEn control
pins should be ramped with or ahead of V
CCB
, this will
guard against bus contentions and oscillations as all A-Port
and B Port outputs will be disabled. To ensure the high
impedance state during power up or power down, OE
n
should be tied to V
CCB
through a pull up resisto r. The mini-
mum value of the resistor is determined by the current
sourcing capability of t he driver. Second, the T/R
n
control
pins should be placed at logic low (0V) level, this will
ensure that the B-sid e b us pi ns are co nfig ure d a s i n put s to
help guard against bus conten tion and oscillation s. B-side
Data Inputs should be driven to a valid lo gic level (0V or
V
CCB
), this will prevent excessive current draw and oscilla-
tions. V
CCA
can then be powered up after V
CCB
, but should
never exceed the V
CCB
voltage level. Up on completion of
these steps the device can then be configured for the users
desired operation. Following these steps will help to prevent possible damage to the translator device as well as
other system components.
Logic Diagrams
Please note that these diagrams are pro v ided only for the understanding of logic operati ons and should not be use d to es t im at e propagation delays.
Inputs
Outputs
OE
1
T/R
1
L L Bus B0–B7 Data to Bus A0–A
7
L H Bus A0–A7 Data to Bus B0–B
7
H X HIGH Z State on A0–A7, B0–B
7
Inputs
Outputs
OE
2
T/R
2
L L Bus B8–B15 Data to Bus A8–A
15
L H Bus A8–A15 Data to Bus B8–B
15
H X HIGH-Z State on A8–A15, B8–B
15
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74VCX164245
Absolute Maximum Ratings(Note 2) Recommended Operating
Conditions
(Note 4)
Note 2: The “Absolute Maximum Ratings ” are those val ues beyond w hich
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the condition s
for actual device operation.
Note 3: I
O
Absolute Maximum Rating must be observed.
Note 4: Unused inputs or I/O pin s mu st be he ld HIG H or L OW. They ma y
not float.
Note 5: Operation requires: V
CCA
≤ V
CCB
DC Electrical Characteristics (1.65V < V
CCA
≤ 1.95V, 2.3V < V
CCB
≤ 2.7V)
Supply Voltage
V
CCA
−0.5V to V
CCB
V
CCB
−0.5V to 4.6V
DC Input Voltage (V
I
) −0.5V to +4.6V
DC Output Voltage (V
I/O
)
Outputs 3-STATE −0.5V to +4.6V
Outputs Active (Note 3)
An −0.5V to V
CCA
+ 0.5V
Bn −0.5V to V
CCB
+ 0.5V
DC Input Diode Current (I
IK
)
V
I
< 0V −50 mA
DC Output Diode Current (I
OK
)
V
O
< 0V −50 mA
V
O
> V
CC
+50 mA
DC Output Source/Sink Current ±50 mA
(I
OH/IOL
)
DC V
CC
or Ground Current ±100 mA
Supply Pin (I
CC
or Ground)
Storage Temperature (T
STG
) −65°C to +150°C
Power Supply (Note 5)
V
CCA
1.65V to 2.7V
V
CCB
2.3V to 3.6V
Input Voltage (V
I
) @ OE, T/R 0V to V
CCB
Input/Output Voltage (V
I/O
)
A
n
0V to V
CCA
B
n
0V to V
CCB
Output Current in IOH/I
OL
V
CCA
= 2.3V to 2.7V ±18 mA
V
CCA
= 1.65V to 1.95V ±6 mA
V
CCB
= 3.0V to 3.6V ±24 mA
V
CCB
= 2.3V to 2.7V ±18 mA
Free Air Operating Temperature (T
A
) −40°C to +85°C
Minimum Input Edge Rate (∆t/∆V)
V
IN
= 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Symbol Parameter Conditions
V
CCA
(V)
V
CCB
(V)
Min Max Units
V
IHA
HIGH Level Input Voltage A
n
1.65−1.95 2.3−2.7 0.65 x V
CC
V
V
IHB
Bn, T/R, OE
1.65−1.95 2.3−2.7 1.6 V
V
ILA
LOW Level Input Voltage A
n
1.6−1.95 2.3−2.7 0.35 x V
CC
V
V
ILB
Bn, T/R, OE
1.65−1.95 2.3−2.7 0.7 V
V
OHA
HIGH Level Output Voltage IOH = −100 µA1.65−1.95 2.3−2.7 V
CCA
−0.2
V
IOH = −6 mA 1.65 2.3−2.7 1.25
V
OHB
HIGH Level Output Voltage IOH = −100 µA1.65−1.95 2.3−2.7 V
CCB
−0.2
V
IOH = −18 mA 1.65−1.95 2.3 1.7
V
OLA
LOW Level Output Voltage IOL = 100 µA1.65−1.95 2.3−2.7 0.2
V
IOL = 6 mA 1.65 2.3−2.7 0.3
V
OLB
LOW Level Output Voltage IOL = 100 µA1.65−1.95 2.3−2.7 0.2
V
IOL = 18 mA 1.65−1.95 2.3 0.6
I
I
Input Leakage Current @ OE, T/R
0V ≤ VI ≤ 3.6V 1.65−1.95 2.3−2.7 ±5.0 µA
I
OZ
3-STATE Output Leakage 0V ≤ VO ≤ 3.6V
1.65−1.95 2.3−2.7 ±10 µA
OE = V
CCB
VI = VIH or V
IL
I
OFF
Power OFF Leakage Current 0≤ (VI, VO) ≤ 3.6V 0 0 10 µA
I
CCA/ICCB
Quiescent Supply Current, An = V
CCA
or GND
1.65−1.95 2.3−2.7 20 µA
per supply, V
CCA
/ V
CCB
Bn, OE, & T/R = V
CCB
or GND
V
CCA
≤ An ≤ 3.6V
1.65−1.95 2.3−2.7 ±20 µA
V
CCB
≤ Bn, OE, T/R ≤ 3.6V
∆I
CC
Increase in ICC per Input, Bn, T/R, OE
VI = V
CCB
– 0.6V 1.65−1.95 2.3−2.7 750 µA
Increase in ICC per Input, A
n
VI = V
CCA
– 0.6V 1.65−1.95 2.3−2.7 750 µA
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