Fairchild Semiconductor 74LVX74MTC, 74LVX74MSCX, 74LVX74M, 74LVX74SJX, 74LVX74SJ Datasheet

May 1993
Revised March 1999

74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

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74LVX74
Low Voltage Dual D-Type Positive Edge-Triggered

Flip-Flop

General Description

The LVX74 is a dual D-type flip-flop with Asynchronous
Clear and Set in puts and complement ary (Q, Q

) outputs.
Information at the input is tra nsferre d to the output s on the
positive edge of the clock pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
the outputs until the next rising edge of the Clock Pulse
input.

Asynchronous Inputs:

LOW input to S

D

(Set) sets Q to HIGH level

LOW input to C

D

(Clear) sets Q to LOW level

Clear and Set are independent of clock
Simultaneous LOW on C

D

and SD makes both Q and Q

HIGH

Features

■ Input voltage level translation from 5V to 3V

■ Ideal for low power/low noise 3.3V applications

■ Guaranteed simultaneous switching noise level and

dynamic threshold performance

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending su ffix let te r “X” to the ordering code.

Connection Diagram Pin Descriptions

Order Number Package Number Package Description

74LVX74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
74LVX74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Description

D

1

, D

2

Data Inputs

CP

1

, CP

2

Clock Pulse Inputs

C

D1

, C

D2

Direct Clear Inputs

S

D1

, S

D2

Direct Set Inputs

Q

1

, Q1, Q2, Q

2

Outputs

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74LVX74

Logic Symbols

IEEE/IEC

Truth Table

(Each Half)

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial



= LOW-to-HIGH Clock Transition

Q

0(Q0

) = Previous Q(Q) before LOW-to-HIGH Transition of Clock

Inputs Outputs

S

D

C

D

CP D Q Q

LHXXHL
HLXXLH
LLXXHH
HH



HHL

HH



LLH

HHLXQ

0

Q

0