Fairchild Semiconductor 74LVX163SJX, 74LVX163SJ, 74LVX163MX, 74LVX163MTCX, 74LVX163MTC Datasheet

October 1996
Revised March 1999

74LVX163
Low Voltage Synchronous Binary Counter with

Synchronous Clear

74LVX163 Low Voltage Synchronous Binary Counter with Synchronous Clear

General Description

The LVX163 is a synchronous modulo-16 bi nary counter.
This device is synchronously pre settable for applic ation in
programmable dividers and has two types of Count Enable
inputs plus a T erminal Count output for versatility in forming
multistage counters. The CLK input is active on the rising
edge. Both PE
els. Presetting is synchronou s to rising edge of the CLK
and the Clear function of the LVX163 is synchronous to the
CLK. Two enable inputs (CEP and CET) and Car ry Outp ut
are provided to en able easy casc ading of coun ters, which

and MR inputs are active o n low logic lev-

facilitates easy implementation of n-bit counters without
using external gates.

The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.

Features

■ Input voltage level translation from 5V to 3V

■ Ideal for low power/low noise 3.3V applications

■ Guaranteed simultaneous switching noise and dynamic

threshold performance

Ordering Code:

Order Number Package Number Package Description

74LVX163M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74LVX163SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Description

Names

CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock Pulse Input
MR
P

0–P3

PE
Q

0–Q3

TC Terminal Count Output

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Synchronous Master Reset Input
Parallel Data Inputs
Parallel Enable Inputs
Flip-Flop Outputs

Functional Description

The LVX163 counts in modulo-16 binary sequence. From
state 15 (HHHH) it increments to state 0 (LLLL). The clock
inputs of all flip-flops a re driven in pa rallel through a clock

74LVX163

buffer. Thus all changes of the Q outputs occur as a result
of, and synchronous with , the LOW-to-HIGH transition of
the CP input signal. The circuits have four fundamental
modes of operation , in order of precedence : synchronous
reset, parallel load, count-up and hold. Four control

inputs—Synchronous Reset (MR
Count Enable Parallel (CEP) and Count Enable Trickle
(CET)—determine th e mode o f operation , as shown in the
Mode Select Table. A LOW signal on MR
ing and parallel loading and allo ws all outputs to go LOW
on the next rising edge of CP. A LOW signal on PE
rides counting and allows information on the Parallel Data

) inputs to be loaded into the flip-flops on the next rising

(P

n

edge of CP. With PE

and MR HIGH, CEP and CET permit
counting when both are HIGH. Conversely, a LOW signal
on either CE P or CET inhibits counting.

The LVX163 uses D-type edge-triggered flip-flops and
changing the MR

, PE, CEP and CET inputs when the CP is
in either state does not cause errors, provided that the rec­ommended setup and hold times, with respect to the rising
edge of CP, are observed.

The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchro­nous multis tage counters, the TC outputs can be used with
the CEP and CET inputs in two different ways.

Figure 1

shows the connections for simple r ipple carry, in
which the clock period must b e longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup time
sets the upper limi t on clock frequency. For faster clock
rates, the carry lookah ead connections sh own in
are recommended. In this scheme the ri p ple de lay thr oug h

), Parallel Enable (PE),

overrides count-

over-

Figure 2

the intermediate stages commences with the same clock
that causes the first stage to tick over from m ax to min in
the Up mode, or m in to m ax in th e D own mo de, to start it s
final cycle. Since this final cycle ta kes 16 clocks to com­plete, there is plenty of time for the ripple to progress
through the intermediate stages. The critical timing that lim­its the clock period is th e CP to TC
plus the CEP

to CP setup time of the last stage. The TC

delay of the first stage

output is subject t o decoding spikes due to intern al race
conditions and is th erefore n ot recommen ded for u se as a
clock or asynchronous reset for flip-flops, registers or
counters. When the Parallel Enable (PE
lel data outputs O

are active and follow the flip-flop Q

0–O3

outputs. A HIGH signal on PE

) is LOW, the paral-

forces O0–O3 to the High

impedance state but does not prevent cou nting, load ing or
resetting.

Logic Equations: Count Enable = CEP • CET • PE

TC = Q0 • Q1 • Q2 • Q3 • CET

Mode Select Table

PE CET CEP Action on the Rising

MR



Clock Edge (

)

L X X X Reset (Clear)
H L X X Load (P

→ Qn)

n

H H H H Count (Increment)
H H L X No Change (Hold)
H H X L No Change (Hold)

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial



= LOW-to-HIGH Clock Transition

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State Diagram

74LVX163

FIGURE 1.

FIGURE 2.

Block Diagram

Please note that this d iagram is provided only f or t he understanding of logic operations and shou ld not be used to estimate propagation delays.

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