Fairchild Semiconductor 74LVX161284AMTX Datasheet

June 1999
Revised July 2000

74LVX161284A
Low Voltage IEEE 161284 Translating Transceiver

74LVX161284A Low Voltage IEEE 161284 Translating Transceiver

General Description

The LVX161284A contains eight bid irectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard, with the exception of output slew rate,
and is intended to be used in an Extended Capabilities Port
mode (ECP). The pinout allows for easy connection from
the Peripheral (A-side) to the Host (cable side).

Outputs on the cable si de can be configured to be either
open drain or high d rive (
separate power supply pin (V

puts to be driven by a higher supply voltage than the
A-side. The pull-up and pull-down series termination resis­tance of these outputs o n the cable side is optimized to
drive an external cabl e. In a ddit io n, all i np uts ( exce pt HL H)
and outputs on the cable side contain internal pull-up resis­tors connected to the V

termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive

CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A

pins.

± 14 mA) and are con nected t o a

cable) to allow these out-

CC

cable supply to provide pr oper

CC

1–A8/B1–B8

transceiver

Features

■ Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
with the exception of output slew rate

■ Translation capability allows outputs on the cable side to
interface with 5V signals

■ All inputs have hysteresis to prov ide noise margin

■ B and Y output resistance optimized to drive external

cable

■ B and Y outputs in high impedance mode during power
down

■ Inp uts and outputs on cable side have internal pull-up
resistors

■ Flow-through pin configuration allows easy interface
between the “Peripheral and Host”

■ Replaces the function of two (2) 74ACT1284 devices

Ordering Code

Order Number

74LVX161284AMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering co de.

Package
Number

Package Description

Connection Diagram Pin Descriptions

Pin Names Description

HD High Drive Enable Input (Active HIGH)
DIR Direction Control Input
A

1–A8

B

1–B8

A

9–A13

Y

9–Y13

A

14–A17

C

14–C17

PLH

IN

PLH Peripheral Logic HIGH Output
HLH

IN

HLH Host Logic HIGH Output

Inputs or Outputs
Inputs or Outputs
Inputs
Outputs
Outputs
Inputs
Peripheral Logic HIGH Input

Host Logic HIGH Input

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Logic Symbol

74LVX161284A

Truth Table

Note 1: Y9–Y13 Open Drain Outputs
Note 2: B

Open Drain Outputs

1–B8

Inputs Outputs

DIR HD

LLB

Data to A1–A8, and

1–B8

A

Data to Y9–Y13 (Note 1)

9–A13

Data to A14–A

C

14–C17

17

PLH Open Drain Mode

LHB

Data to A1–A8, and

1–B8

Data to Y9–Y

A

9–A13

C14–C17 Data to A14–A

13

17

HLA1–A8 Data to B1–B8 (Note 2)

Data to Y9–Y13 (Note 1)

A

9–A13

C

Data to A14–A

14–C17

17

PLH Open Drain Mode

HHA

Data to B1–B

1–A8

8

A9–A13 Data to Y9–Y
C14–C17 Data to A14–A

13

17

Logic Diagram

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Absolute Maximum Ratings(Note 3) Recommended Operating

Supply Voltage

V

CC

V

CC—Cable

V

CC—Cable

Must Be ≥ V

CC

−0.5V to +4.6V

−0.5V to +7.0V

Input Voltage (VI)—(Note 4)

A

, PLHIN, DIR, HD −0.5V to VCC + 0.5V

1–A13

, C14–C17, HLH

B

1–B8

B

, C14–C17, HLH

1–B8

IN
IN

−0.5V to +5.5V (DC)

−2.0V to +7.0V*

*40 ns Transient

Output Voltage (V

A

, A14–A17, HLH −0.5V to VCC +0.5V

1–A8

B

, Y9–Y13, PLH −0.5V to +5.5V (DC)

1–B8

, Y9–Y13, PLH −2.0V to +7.0V*

B

1–B8

)

O

*40 ns Transient

DC Output Current (I

, HLH ±25 mA

A

1–A8

B

, Y9–Y

1–B8

)

O

13

±50 mA

PLH (Output LOW) 84 mA
PLH (Output HIGH) −50 mA

Input Diode Current (I

DIR, HD, A

9–A13

Output Diode Current (I

A

, A14–A17, HLH ±50 mA

1–A8

B

, Y9–Y13, PLH −50 mA

1–B8

DC Continuous V
Storage Temperature

)—(Note 4)

IK

, PLH, HLH, C14–C

)

OK

or Ground Current ±200 mA

CC

17

−20 mA

−65°C to +150°C

ESD (HBM) Last Passing Voltage 2000V

Conditions

Supply Voltage

V

CC

V

CC—Cable

DC Input Voltage (V
Open Drain Voltage (VO) 0V to 5.5V
Operating Temperature (T

Note 3: Absolute Maximum continuous ratings are those values beyond
which damage t o the device ma y occur. Exposure to t hese condition s or
conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute maximum rated conditions is not
implied.

Note 4: Either voltage lim it or c urrent limit is sufficient to protect inputs.

)0V to V

I

) −40°C to +85°C

A

74LVX161284A

3.0V to 3.6V

3.0V to 5.5V

CC

DC Electrical Characteristics

Symbol Parameter

V

IK

V

IH

V

IL

∆V

V

OH

Input Clamp
Diode Voltage
Minimum An, Bn, PLHIN, DIR, HD 3.0–3.6 3.0–5.5 2.0

Input Voltage HLH
Maximum An, Bn, PLHIN, DIR, HD 3.0–3.6 3.0–5.5 0.8

Input Voltage HLH
Minimum Input An, Bn, PLHIN, DIR, HD 3.3 5.0 0.4

T

Hysteresis C

Minimum HIGH An, HLH 3.0 3.0 2.8
Level Output 3.0 3.0 2.4 IOH = −4 mA
Voltage Bn, Y

n

IN

n

IN

n

HLH

IN

n

Bn, Y

n

PLH 3.15 3.15 3.1 IOH = −500 µA

V

CCVCC—CableTA

(V) (V) Guaranteed Limits

3.0 3.0 −1.2 V I

3.0–3.6 3.0–5.5 2.3

3.0–3.6 3.0–5.5 2.6

3.0–3.6 3.0–5.5 0.8

3.0–3.6 3.0–5.5 1.6

3.3 5.0 0.8 V

3.3 5.0 0.2 V

3.0 3.0 2.0 IOH = −14 mA

3.0 4.5 2.23 IOH = −14 mA

= −40°C to +85°C

Units Conditions

= −18 mA

i

VHIGH Level C

VLOW Level C

+

−

V

–V

T

T

+

V

V

−

–V

T

T

+

−

–V

T

T

IOH = −50 µA

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