Fairchild Semiconductor 74LVTH162244MTX, 74LVTH162244MTD, 74LVTH162244MEX, 74LVTH162244MEA, 74LVT162244MTDX Datasheet

March 1999
Revised June 1999

74LVT162244 • 74LVTH162244
Low Voltage 16-Bit Buffer/Line Driver with 3-STATE

Outputs and 25Ω Series Resistors in the Outputs

74LVT162244 • 74LVTH162244 Low Voltage 16-Bit Buff er/Line Driv er wit h 3-STATE Out puts and 25Ω Series Resis-

tors in the Outputs

General Description

The LVT162244 and LVTH162244 contain sixteen non­inverting buffers with 3-STATE outputs designed to be
employed as a memor y an d ad dr ess d river, clock driver, or
bus oriented transmitter/re ceive r. The device is nibble con­trolled. Individual 3-S TATE control inputs can b e shorted
together for 8-bit or 16-bit operation.

The LVT162244 and LVTH162244 are designed with
equivalent 25Ω series resistance in both the HIGH and
LOW states of the output. This design reduces line noise in
applications such as memory address drivers, cl ock driv­ers, and bus transceivers/transmitters.

The LVTH162244 data inputs includ e bushold, eliminat ing
the need for external pull-up resistors to hold unused
inputs.

These buffers and line drivers are designed for low-voltage
(3.3V) V

TTL interface to a 5V en vironment. The LVT162244 and
LVTH162244 are fabricated with an advanced BiCMOS

applications, but with the capability to provide a

CC

technology to achieve high speed operation si milar to 5V
ABT while maintaining a low power dissipation.

Features

■ Input and output interface capability to systems at
5V V

CC

■ Bushold data inputs elimina te the nee d for exte rnal pull­up resistors to hold unused inputs (74LVTH162244),
also available without bushold feature (74LVT162244).

■ Live insertion/extraction per mitt ed

■ Power Up/Down high impedance provides glitch-free

bus loading

■ Outputs include equivalen t series resistance of 25Ω to
make external termination resistors unnecessary and
reduce overshoot and undershoot

■ Functionally compatible with the 74 series 162244

■ Latch-up performance exce eds 500 mA

Ordering Code:

Order Number

74LVT162244MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVT162244MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH162244MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVTH162244MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Device also available in Tape and Reel. Specify by appending su ffix le tter “X” to the ordering co de.

Package

Number

Package Description

Logic Symbol

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Connection Diagram Pin Descriptions

Pin Names Description

OE

n

I

0–I15

O

0–O15

Truth Table

Inputs Outputs

OE

1

LL L
LH H

74LVT162244 • 74LVTH162244

HX Z

OE

2

LL L
LH H
HX Z

OE

3

LL L
LH H
HX Z

OE

4

LL L
LH H
HX Z

Output Enable Inputs (Active LOW)

Inputs
Outputs

I0–I

I4–I

I8–I

I12–I

3

7

11

15

O0–O

O4–O

O8–O

O12–O

3

7

11

15

Functional Description

The LVT162244 and LVTH162244 contain sixteen non-inverting buffers with 3-STA TE outputs. The device is nibble (4 bits)
controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to
obtain full 16-bit operation.

Logic Diagram

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