Fairchild Semiconductor 74LVTH162240MTX, 74LVTH162240MTD, 74LVTH162240MEX, 74LVTH162240MEA Datasheet

June 1999
Revised June 1999

74LVT162240 • 74LVTH162240
Low Voltage 16-Bit Inverting Buffer/Line Driver

with 3-STATE Outputs and
25Ω Series Resistors in the Outputs

74LVT162240 • 74LVTH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25Ω

Series Resistors in the Outputs

General Description

The LVT162240 and LVTH162240 contain sixteen inverting
buffers with 3-STATE outputs designed to be employe d as
a memory and address d rive r, clock driver, or bus oriented
transmitter/receiver. The device is nibble contr olled. Indi­vidual 3-STATE control inputs ca n be shorted toge ther for
8-bit or 16-bit operation.

The LVT162240 and LVTH162240 are designed with
equivalent 25Ω series resistance in both the HIGH and
LOW states of the output. This design reduces line noise in
applications such as memory address drivers, cl ock driv­ers, and bus transceivers/transmitters.

The LVTH162240 data inputs includ e bushold, eliminat ing
the need for external pull-up resistors to hold unused
inputs.

These inverting buffers and li ne drivers are designed for
low-voltage (3.3V) V

to provide a TTL interface to a 5V environment. The
LVT162240 and LVTH162240 are fabricated with an

applications, but with the capability

CC

advanced BiCMOS technology to achieve high speed oper­ation similar to 5V ABT while maintaining a low power dis­sipation.

Features

■ Input and output interface capability to systems at
5V V

CC

■ Outputs include equivalen t series resistance of 25Ω to
make external termination resistors unnecessary and
reduce overshoot and undershoot

■ Bushold data inputs elimina te the nee d for exte rnal pull­up resistors to hold unused inputs (74LVTH162240),
also available without bushold feature (74LVT162240).

■ Live insertion/extraction per mitt ed

■ Power Up/Down high impedance provides glitch-free

bus loading

■ Functionally compatible with the 74 series 162240

■ Latch-up performance exce eds 500 mA

Ordering Code:

Order Number Package Number Package Description

74LVT162240MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVT162240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH162240MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVTH162240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code .

Logic Symbol Pin Descriptions

Pin Names Description

OE

n

I

0–I15

O

0–O15

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Output Enable Inputs (Active LOW)
Inputs
3-STATE Outputs

Connection Diagram Truth Table

74LVT162240 • 74LVTH162240

H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial Z = High Impedance

Inputs Outputs

OE

1

LLH
LHL
HXZ

I0–I

3

O0–O

3

Inputs Outputs

OE

2

LLH
LHL
HX Z

I4–I

7

O4–O

7

Inputs Outputs

OE

3

LLH
LHL
HXZ

I8–I

11

O8–O

11

Inputs Outputs

OE

4

LLH
LHL
HXZ

I12–I

15

O12–O

15

Functional Description

The LVT162240 and LVTH162240 contain sixteen inverting
buffers with 3-STATE standard outputs. The de vice is nib­ble (4 bits) controlle d with each nibble functioning identi­cally, but independent of the other. The control pins may be
shorted together to obtain full 16-bit operation. The 3-

STATE outputs are controlled by an Output Enable (OEn)
input for each nibble. When OE
2-state mode. Wh en OE

is LOW, the outputs are in

n

is HIGH, the outputs are in the

n

high impedance mode, but this does not interfere with
entering new data into the inputs.

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and shou ld not be used to estimate propagation delays.

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