Fairchild Semiconductor 74LVQ573SJX, 74LVQ573SJ, 74LVQ573SCX, 74LVQ573SC, 74LVQ573QSCX Datasheet

74LVQ573
Low Voltage Octal Latch with 3-STATE Outputs

General Description

The LVQ573 is a high-speed octal latch with buffered com­mon Latch Enable (LE) and buffered common Output Enable
(OE) inputs. The LVQ573 is functionally identical to the
LVQ373but with inputs and outputs on opposite sides of the
package.

Features

n Ideal for low power/low noise 3.3V applications
n Implements patented EMI reduction circuitry
n Available in SOIC JEDEC, SOIC EIAJ, and QSOP

packages

n Guaranteed simultaneous switching noise level and

dynamic threshold performance

n Improved latch-up immunity
n Guaranteed incident wave switching into 75Ω
n 4 kV minimum ESD immunity

Ordering Code:

Order Number Package Number Package Description

74LVQ573SC M20B 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC
74LVQ573SJ M20D 20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ
74LVQ573QSC MQA20 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols Connection Diagram

Pin Descriptions

Pin Names Description

D

0–D7

Data Inputs
LE Latch Enable Input
OE

3-STATE Output Enable Input
O

0–O7

3-STATE Latch Outputs

DS011361-1

IEEE/IEC

DS011361-2

Pin Assignment for

SOIC and QSOP

DS011361-3

May 1998

74LVQ573 Low Voltage Octal Latch with 3-STATE Outputs

© 1998 Fairchild Semiconductor Corporation DS011361 www.fairchildsemi.com

Truth Table

Inputs Outputs

OE

LE D O

n

LHH H
LHL L
LLX O

0

HXX Z

H

=

HIGH Voltage
L=LOW Voltage
Z=High Impedance
X=Immaterial
O

0

=

Previous O

0

before HIGH-to-LOW transition of Latch Enable

Functional Description

The LVQ573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D

n

inputs enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its D-type input changes. When LE is LOW the
latches store the information that was present on the D-type
inputs a setup time preceding the HIGH-to-LOW transition of
LE. The 3-STATE buffers are controlled by the Output En­able (OE) input. When OE is LOW, the buffers are enabled.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data into
the latches.

Logic Diagram

DS011361-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

www.fairchildsemi.com 2