Fairchild Semiconductor 74LVQ273SJX, 74LVQ273SJ, 74LVQ273SCX, 74LVQ273SC, 74LVQ273QSCX Datasheet
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74LVQ273
Low Voltage Octal D-Type Flip-Flop
General Description
The LVQ273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The device is usefulforapplicationswherethetrueoutputonly is required and the Clock and Master Reset are common to all
storage elements.
Features
n Ideal for low power/low noise 3.3V applications
n Implements patented EMI reduction circuitry
n Available in SOIC JEDEC, SOIC EIAJ and QSOP
packages
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75Ω
n 4 kV minimum ESD immunity
Ordering Code:
Order Number Package Number Package Description
74LVQ273SC M20B 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC
74LVQ273SJ M20D 20-Lead Shrink Molded Small Outline Package, SOIC EIAJ
74LVQ273QSC MQA20 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol Connection Diagram
Pin Descriptions
Pin Names Description
D
0–D7
Data Inputs
MR
Master Reset
CP Clock Pulse Input
Q
0–Q7
Data Outputs
DS011358-1
IEEE/IEC
DS011358-2
Pin Assignment for
SOIC and QSOP
DS011358-3
April 1998
74LVQ273 Low Voltage Octal D-Type Flip-Flop
© 1998 Fairchild Semiconductor Corporation DS011358 www.fairchildsemi.com
Absolute Maximum Ratings (Note 1)
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=
−0.5V −20 mA
V
I
=
V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=
−0.5V −20 mA
V
O
=
V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC+ 0.5V
DC Output Source
or Sink Current (I
O
)
±
50 mA
DC V
CC
or Ground Current
(I
CC
or I
GND
)
±
400 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
DC Latch-up Source or
Sink Current
±
300 mA
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
) 2.0V to 3.6V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (VO) 0VtoV
CC
Operating Temperature (TA) −40˚C to +85˚C
Minimum Input Edge Rate ∆V/∆t
V
IN
from 0.8V to 2.0V
V
CC
@
3.0V 125 mV/ns
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol Parameter V
CC
T
A
=
+25˚C T
A
=
−40˚C to +85˚C Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum High Level 3.0 1.5 2.0 2.0 V V
OUT
=
0.1V
Input Voltage or V
CC
− 0.1V
V
IL
Maximum Low Level 3.0 1.5 0.8 0.8 V V
OUT
=
0.1V
Input Voltage or V
CC
− 0.1V
V
OH
Minimum High Level 3.0 2.99 2.9 2.9 V I
OUT
=
−50 µA
Output Voltage 3.0 2.58 2.48 V V
IN
=
V
IL
or VIH(Note 3)
I
OH
=
−12 mA
V
OL
Maximum Low Level 3.0 0.002 0.1 0.1 V I
OUT
=
50 µA
Output Voltage 3.0 0.36 0.44 V V
IN
=
V
IL
or VIH(Note 3)
I
OL
=
12 mA
I
IN
Maximum Input 3.6
±
0.1
±
1.0 µA V
I
=
V
CC
, GND
Leakage Current
I
OLD
Minimum Dynamic 3.6 36 mA V
OLD
=
0.8V Max (Note 5)
I
OHD
Output Current (Note 4) 3.6 −25 mA V
OHD
=
2.0V Min (Note 5)
I
CC
Maximum Quiescent 3.6 4.0 40.0 µA V
IN
=
V
CC
or GND
Supply Current
V
OLP
Quiet Output 3.3 0.4 0.8 V (Notes 6, 7)
Maximum Dynamic V
OL
V
OLV
Quiet Output 3.3 −0.3 −0.8 V (Notes 6, 7)
Minimum Dynamic V
OL
V
IHD
Maximum High Level 3.3 1.7 2.0 V (Notes 6, 8)
Dynamic Input Voltage
V
ILD
Maximum Low Level 3.3 1.6 0.8 V (Notes 6, 8)
Dynamic Input Voltage
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V
ILD
), 0V to threshold (V
IHD
),
f=1 MHz.
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