Fairchild Semiconductor 74LCX32652 Datasheet
August 2001
Revised August 2001
74LCX32652
Low Voltage Transceiver/Regis ter
with 5V Tolerant Inputs and Outputs (Preliminary)
Preliminary
74LCX32652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs (Preliminary)
General Description
The LCX32652 contains thirty-two non-inverting bidirectional bus transceivers with 3-STATE outputs providing
multiplexed transmission of da ta di re ctly from the i npu t bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to the HIGH logic level. Each byte has separate cont rol
inputs which can be sho rted together for full 32-bit oper ation. Output Enable pins (OEAB
control the transceiver function (see Functional Description).
The LCX32652 is de signed for low- voltage (2.5V or 3.3V)
V
applications with capability of interfacing to a 5V signal
CC
environment.
The LCX32652 is fabricated with an advanced CMOS tech-
nology to achieve high s peed operation while maintaining
CMOS low power dissipation.
, OEBAn) are provided to
n
Features
■ 5V tolerant inputs and outputs
■ 2.3V–3.6V V
■ 5.7 ns t
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■
±24 mA output drive (V
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exce eds 500 mA
■ ESD performance:
Human body model
Machine model
■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
(Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC and OE tied to GND through a resistor: the minimum
value or the resis tor i s det erm ined by t he c urren t-s ourc ing c apab ility of the
driver.
specifications provided
CC
max (VCC = 3.3V), 20 µA ICC max
PD
> 200V
Ordering Code:
Order Number Package Number Package Description
74LCX32652GX
(Note 2)
Note 2: BGA package available in Tape and Reel only.
BGA114A
(Preliminary)
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
= 3.0V)
CC
> 2000V
© 2001 Fairchild Semiconductor Corporation DS500634 www.fairchildsemi.com
Preliminary
Connection Diagram
Pin Assignment for FBGA
74LCX32652
(Top Thru View)
Pin Descriptions
Pin Names Description
1A
- 1A
0
2A
- 2A
0
1B0 - 1B
2B
- 2B
0
Data Register A Inputs/3-STATE Outputs
15
15
Data Register B Inputs/3-STATE Outputs
15
15
CPABn, CPBAnClock Pulse Inputs
, SBA
SAB
n
OEAB
, OEBAnOutput Enable Inputs
n
n
Select Inputs
NC No Connect
FBGA Pin Assignments
123 456
A 1A
B 1A21A1OEAB1OEBA11B11B
C 1A41A3GND GND 1B31B
D 1A61A5V
E 1A81A7GND GND 1B71B
F 1A101A9GND GND 1B91B
G 1A121A
H 1A131A14GND GND 1B141B
J 1A15SAB2CPAB2CPBA2SBA21B
K NC CPAB3OEAB2OEBA2CPBA3NC
L 2A
M 2A22A1GND GND 2B12B
N 2A42A3V
P 2A62A5GND GND 2B52B
R 2A82A7GND GND 2B72B
T 2A102A9V
U 2A122A11GND GND 2B112B
V 2A132A14CPAB4CPBA42B142B
W 2A15SAB4OEAB4OEBA4SBA42B
SAB1CPAB1CPBA1SBA11B
0
V
CC
CC
11VCC
SAB3OEAB3OEBA3SBA32B
0
V
CC
V
CC
CC
V
CC
CC
1B51B
1B111B
2B32B
2B92B
0
2
4
6
8
10
12
13
15
0
2
4
6
8
10
12
13
15
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Preliminary
Truth Table
(Note 3)
OEAB
OEBA1CPAB1CPBA1SAB1SBA11A0 thru 1A71B0 thru 1B
1
L H H or L H or L X X Input Input Isolation
LH
XH
HH
LXH or L
LL
L L X X X L Output Input Real-Time B Data to A Bus
L L X H or L X H Store B Data to A Bus
H H X X L X Input Output Real-Time A Data to B Bus
H H H or L X H X Stored A Data to B Bus
H L H or L H or L H H Output Output Stored A Data to B Bus and
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clo c k Transit ion
Note 3: Data I/O paths (1A and 1B: 0 - 7) is sh own . This a lso ap pli es to dat a I/O (1 A a nd 1B: 8 - 15) an d #2 co ntro l pins, to data (2A an d 2B : 0 - 7) an d #3
control pins, to data (2A and 2B: 8 - 15) and #4 control pins.
Note 4: The data output functions may be enabled or dis abled by various sig nals at OEAB or OEBA
i.e., data at the bus pins wi ll be stored on every LO W-to-HIGH transition on t he clock inputs.
Inputs Inputs/Outputs (Note 4)
7
H or L X X Input Not Specified Store A, Hold B
X X Store A and B Data
X X Input Output Store A in Both Registers
X X Not Specified Input Hold A, Store B
X X Output Input Store B in Both Registers
inputs. Data input functions are always enabled,
Operating Mode
Stored B Data to A Bus
74LCX32652
3 www.fairchildsemi.com
Functional Description
In the transceiver mo de, data pr esent at the HIGH i mpedance port may be stored in either the A or B register or
both.
The select (SAB
real-time.
74LCX32652
The examples below demonstrate the four fundamental
bus-management functions that ca n be per forme d with the
74LCX32652 for data register I/O 1A and 1B: 0 - 7.
, SBAn) controls can multiplex sto red an d
n
Preliminary
Data on the A or B data bus, or both can be stored in the
internal D flip-flop by LOW-to-HIGH transitions at the
appropriate Clock Inputs (CPAB
the Select or Output Ena ble Inputs. When SAB and S BA
are in the real time transfer mode, it is also possible to
store data without using the internal D flip-flops by simultaneously enabling OE AB
n
each Output reinfor ces its Input. T hus when al l other data
sources to the two sets of bus line s are in a HIGH impe dance state, each set of bus lines will remain at its last state.
, CPBAn) regardless of
n
and OEBAn. In this configuration
Real-Time
Transfer Bus B to Bus A
OEAB
OEBA1CPAB1CPBA1SAB1SBA
1
1
OEAB1OEBA1CPAB1CPBA1SAB1SBA
Real-Time
Transfer Bus A to Bus B
LLXXXL HHXXLX
Transfer Storage
Storage
Data to A or B
1
OEAB
OEBA1CPAB1CPBA1SAB1SBA
1
1
H L H or L H or L H H X H
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OEAB1OEBA1CPAB1CPBA1SAB1SBA
XXX
LXX
LH
XX
XX
1
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