Fairchild Semiconductor 74LCX32374 Datasheet
January 2001
Revised August 2001
74LCX32374
Low Voltage 32-Bit D-Type Flip-Flop
with 5V Tolerant Inputs and Outputs (Preliminary)
Preliminary
74LCX32374 Low Voltage 32-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs (Preliminary)
General Description
The LCX32374 contains thirty-two non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus oriented applications. The dev ice is byte controlled. A buffered clock (CP) and Output E nable (OE
each byte and can be shorted together for full 32-bit operation.
The LCX32374 is desi gned for low vol tage (2.5V or 3.3V )
V
applications with capability of interfacing to a 5V signal
CC
environment.
The LCX32374 is fabricated with an advanced CMOS tech-
nology to achieve high s peed operation while maintaining
CMOS low power dissipation.
) are common to
Features
■ 5V tolerant inputs and outputs
■ 2.3V–3.6V V
■ 6.2 ns t
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■
±24 mA output drive (V
■ Uses patented noise/EMI reductio n circuitr y
■ Latch-up performance exce eds 500 mA
■ ESD performance:
Human body model
Machine model
■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
(Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up res istor: the m inimu m value or t he
resistor is determin ed by the current-sourc ing capability of the driver.
specifications provided
CC
max (VCC = 3.3V), 20 µA ICC max
PD
> 200V
Ordering Code:
Order Number Package Number Package Description
74LCX32374GX
(Note 2)
Note 2: BGA device available in Tape and Reel only.
BGA96A
(Preliminary)
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
Logic Symbol
= 3.0V)
CC
> 2000V
© 2001 Fairchild Semiconductor Corporation DS500427 www.fairchildsemi.com
Preliminary
Connection Diagram
74LCX32374
(Top Thru View)
Functional Description
The LCX32374 consists of thirty-two edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control
pins can be shor ted tog eth er to ob tai n fu ll 32 -b it o per ati o n.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flo ps within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requir ements on the LOW-to-HIG H Clock (CP
transition. With the Output Enable (OE
tents of the flip-flops a re available at the outputs. When
OE
is HIGH, the outputs go to the high imped ance state.
n
Operation of the OE
input does not affect the st ate of the
n
flip-flops.
) LOW, the con-
n
Pin Descriptions
Pin Names Descriptio n
OE
CP
I
0–I31
O
0–O31
n
n
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
Outputs
FBGA Pin Assignments
123456
A O
O0OE1CP1I
1
B O3O2GND GND I
C O5O4V
D O7O6GND GND I
E O
O8GND GND I
9
F O11O10V
G O13O12GND GND I
H O14O15OE2CP2I
J O
17O16
K O19O18GND GND I
L O21O20V
M O23O22GND GND I
N O25O24GND GND I
P O27O26V
R O29O28GND GND I
T O30O31OE4CP4I
)
n
Truth Table
Inputs Outputs
CP
n
LL X O
XH X Z
X = Immaterial
Z = High Impedance
= Previous O0 before HIGH-to-LOW of CP
O
0
OE
n
LH H
LL L
0
2
CCVCCI4
6
8
CCVCCI10I11
12I13
15I14
OE3CP3I
CCVCCI20I21
CCVCCI26I27
I
n
16I17
18I19
22I23
24I25
28I29
31I30
O
I
1
I
3
I
5
I
7
I
9
n
0
www.fairchildsemi.com 2
Logic Diagrams
Preliminary
74LCX32374
Byte 1 (0:7)
Byte 2 (8:15)
Byte 3 (16:23)
Byte 4 (24:31)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3 www.fairchildsemi.com