Fairchild Semiconductor 74LCX16652MEA, 74LCX16652CW, 74LCX16652MTDX, 74LCX16652MTD, 74LCX16652MEAX Datasheet
February 1994
Revised April 1999
74LCX16652 Low Voltage T ransceiver/Register with 5V Tolerant Inputs and Outputs
© 1999 Fairchild Semiconductor Corporation DS012005.prf www.fairchildsemi.com
74LCX16652
Low Voltage Transceiver/Register with 5V Tolerant
Inputs and Outputs
General Description
The LCX16652 conta ins s ixteen n on-inve rting bidir ectional
bus transceivers with 3-STATE outputs providing multiplexed transmission of data directly from the input bus or
from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to the HIGH logic level. Output Enable pins (OEAB, OEBA
)
are provided to cont rol the tra nsceiver function (se e Functional Description).
The LCX16652 is de signed for low- voltage (2.5V or 3.3V)
V
CC
applications with capability of interfacing to a 5V signal
environment.
The LCX16652 is fabricated with an advanced CMOS tech-
nology to achieve high spee d operation while mai ntaining
CMOS low power dissipation.
Features
■ 5V tolerant inputs and outputs
■ 2.3V–3.6V V
CC
specifications provided
■ 5.7 ns t
PD
max (VCC = 3.3V), 20 µA ICC max
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ ±24 mA output drive (V
CC
= 3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedan c e state during power up or down, OE
should be tied to VCC and OE tied to GND through a resistor: the minimum
value or the resis tor i s dete rmin ed by the cur ren t-sour cing cap ab ility of the
driver.
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbol Pin Descriptions
Order Number Package Number Package Description
74LCX16652MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LCX16652MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
A
0–A15
Data Register A Inputs/3-STATE Outputs
B
0–B15
Data Register B Inputs/3-STATE Outputs
CPAB
n
, CPBAnClock Pulse Inputs
SAB
n
, SBAnSelect Inputs
OEAB
n
, OEBAnOutput Enable Inputs
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74LCX16652
Connection Diagram
Truth Table
(Note 2)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Note 2: The data output fu nction s may b e enable d or di sabled b y variou s signa ls at OEA B or O EBA
inputs. Data input function s are a lways e nabled, i.e.,
data at the bus pins w ill be stored on every LOW-to -H I GH t ransition on the clock inp ut s . This also applies to data I/O (A and B: 8–15) and #2 control pins.
Inputs Inputs/Outputs
Operating Mode
OEAB
OEBA
1
CPAB1CPBA1SAB1SBA1A0 thru A
7
B0 thru B
7
L H H or L H or L X X Input Input Isolation
LH
X X Store A and B Data
XH
H or L X X Input Not Specified Store A, Hold B
HH
X X Input Output Store A in Both Registers
LXH or L
X X Not Specified Input Hold A, Store B
LL
X X Output Input Store B in Both Registers
L L X X X L Output Input Real-Time B Data to A Bus
L L X H or L X H Store B Data to A Bus
H H X X L X Input Output Real-Time A Data to B Bus
H H H or L X H X Stored A Data to B Bus
H L H or L H or L H H Output Output Stored A Data to B Bus and
Stored B Data to A Bus
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74LCX16652
Functional Description
In the transceiver mode , data present a t the HIGH impe dance port may be sto red in either the A or B register or
both.
The select (SAB
n
, SBAn) controls can multiplex stored and
real-time.
The examples below demonstrate the four fundamental
bus-management fun cti on s t hat c an be performed with the
74LCX16652.
Data on the A or B data bus, or both can be stored in the
internal D flip-flop by LOW-to-HIGH transitions at the
appropriate Clock Inputs (CPAB
n
, CPBAn) regardless of
the Select or Output Enable Inputs. When SAB and SBA
are in the real time transfer mode, it is also possible to
store data without usi ng th e int ern al D f lip -flo ps b y si mu ltaneously enabling OEAB
n
and OEBAn. In this configuration
each Output reinforces its Input. Thu s when all other data
sources to the two sets of bus lin es are in a HIGH imp edance state, each set of bus lines will remain at its last state.
Real-Time
Transfer Bus B to Bus A
Real-Time
Tran sfer Bus A to Bus B
Transfer Storage
Data to A or B
Storage
OEAB
1
OEBA1CPAB1CPBA1SAB1SBA
1
LLXXXL
OEAB1OEBA1CPAB1CPBA1SAB
1
SBA
1
HHXXLX
OEAB1OEBA1CPAB1CPBA1SAB1SBA
1
H L H or L H or L H H
OEAB1OEBA1CPAB1CPBA1SAB1SBA
1
XH
XXX
LXX
XX
LH
XX
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