Fairchild Semiconductor 74FR573SCX, 74FR573SC, 74FR573PC Datasheet

© 1999 Fairchild Semiconductor Corporation DS010903 www.fairchildsemi.com

January 1991
Revised August 1999

74FR573 Octal D-Type Latch with 3-STATE Outputs

74FR573
Octal D-Type Latch with 3-STATE Outputs

General Description

The 74FR573 is a high speed octal latch with buffered
common Latch Enable (LE) and buffered common Output
Enable (OE

) inputs.

This device is functionally identical to the 74F573.

Features

■ Broadside pinout aids in PC layout

■ Functionally identical to the 74F373, 74F573

■ Outputs have current sourcing capability of 15 mA and

current sinking capability of 64 mA

■ Guarante ed pin-to-pin skew

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbol Connection Diagram

Pin Descriptions

Order Number Package Number Package Description

74FR573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74FR573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

OE

Output Enable Input (Active-LOW)
LE Latch Enable Input (Active-HIGH)
D

0–D7

Data Inputs
O

0–O7

3-STATE Latch Outputs

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74FR573

Functional Description

The 74FR573 conta ins eight D-type latches with 3 -STATE
output buffers. When th e latch enable (LE ) input is HIGH,
data on the D

n

inputs enters the latches. In this co ndition

the latches are transparent, i.e., a latch output will chang e
state each time its D input ch anges. Whe n LE is L OW the
latches store the information that was present on th e D
inputs a setup time preceding the HIGH-to-LOW transitio n
of LE. The 3-STATE buffers are controlled by the O utput
Enable (OE

) input. When OE is LOW, the buffers are in the

bi-state mode. When OE

is HIGH the buffers are in the high
impedance mode, but this doe s not interfere with enterin g
new data into the latches.

Function Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

Logic Diagram

Inputs Output

OE

LE D

n

O

n

LHH H
LHL L
LLX O

n − 1

H X X High Z State