Fairchild Semiconductor 74F827SPC, 74F827SCX, 74F827SC Datasheet

© 1999 Fairchild Semiconductor Corporation DS009598 www.fairchildsemi.com

April 1988
Revised August 1999

74F827 • 74F828 10-Bit Buffers/Line Drivers

74F827 • 74F828
10-Bit Buffers/Line Drivers

General Description

The 74F827 and 74F8 28 10-bit bus buffers provide high
performance bus inter face buffering fo r wide dat a/address
paths or buses carrying parity. The 10-bit buffers have
NOR output enables for maximum control flexibility.

The 74F828 is an inverting version of the 74F827.

Features

■ 3-STATE output

■ 74F828 is inverting

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagrams

74F827 74F828

Order Number Package Number Package Description

74F827SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F827SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
74F828SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F828SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

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74F827 • 74F828

Logic Symbols

74F827

IEEE/IEC

74F827

74F828

IEEE/IEC

74F828

Unit Loading/Fan Out

Functional Description

The 74F827 and 7 4F828 are line drivers designed to be
employed as memory address drivers, clock drivers and
bus-oriented transmitters/receivers which provide
improved PC board de nsity. The devices have 3-STATE
outputs controlled by the Output Enable (OE

) pins. The
outputs can sink 64 mA and source 15 mA. Input clamp
diodes limit high-speed termination effects.

Function Table

H = HIGH Voltage level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

OE1, OE

2

Output Enable Input 1.0/1.0 20 µA/−0.6 mA

D

0–D7

Data Inputs 1.0/1.0 20 µA/−0.6 mA

O

0–O7

Data Outputs, 3-STATE 600/106.6 (80) −12 mA/64 mA (48 mA)

Inputs Outputs

OE

D

n

O

n

Function

74F827 74F828

L H H L Transparent
L L L H Transparent
H X Z Z High Z

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74F827 • 74F828

Logic Diagrams

74F827

Please note that this d iagram is provided only f or t he understanding of lo gic operations and should not be used to estimat e propagation delays.

74F828

Please note that this d iagram is provided only f or t he understanding of lo gic operations and should not be used to estimat e propagation delays.