Fairchild Semiconductor 74F779PC, 74F779SCX, 74F779SC Datasheet

© 2000 Fairchild Semiconductor Corporation DS009593 www.fairchildsemi.com

April 1988
Revised March 2000

74F779 8-Bit Bidirectional Binary Counter with 3-STATE Outputs

74F779
8-Bit Bidirectional Binary Counter with 3-STATE Outputs

General Description

The 74F779 is a fully synchronous 8-stage up/down
counter with multiplexed 3-STATE I/O ports for bus-ori­ented applications. All control functions (hold, count up,
count down, synchronous load) are controlled by two mode
pins (S

0

, S1). The device als o f eat ure s ca rr y loo kah ead f or

easy cascading. All state changes are initiated by the rising
edge of the clock.

Features

■ Multiplexed 3-STATE I/O ports

■ Built-in lookahead carry capability

■ Count frequency 100 MHz typ

■ Supply current 80 mA typ

■ Available in SOIC (300 mil only)

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbol Connection Diagram

Order Number Package Number Package Description

74F779SC M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F779PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F779

Unit Loading/Fan Out

Function Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial



= LOW-to-HIGH Clock Transition

(Not LL) means S

0

and S1 should never both be LOW level at the same time.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

I/O0–I/O

7

Data Inputs 0.25/0.33 5 µA/−0.2 mA
Data Outputs 75/15 (12.5) −3 mA/24 mA (20 mA)

S

0

, S

1

Select Inputs 0.25/0.33 5 µA/−0.2 mA

OE

Output Enable Input (Active LOW) 0.25/0.33 5 µA/−0.2 mA

CET

Count Enable Trickle Input (Active LOW) 0.25/0.33 5 µA/−0.2 mA
CP Clock Pulse Input (Active Rising Edge) 0.25/0.33 5 µA/−0.2 mA
TC

Terminal Count Output (Active LOW) 25/12.5 −1 mA/20 mA

S

1

S

0

CET OE CP Function

XXXHXI/O

0

to I/O7 in High Z
X X X L X Flip-Flop Outputs Appear on I/O Lines
LLXH



Parallel Load All Flip-Flops

(Not LL) H X



Hold (TC Held HIGH)

HLLX



Count Up

LHLX



Count Down

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74F779

Logic Diagram

Please note that this d iagram is provided only f or t he understanding of lo gic operations and should not be used to estimat e propagation delays.