Fairchild Semiconductor 74F413PC Datasheet

April 1988
Revised August 1999

74F413
64 x 4 First-In First-Out Buffer Memory with Parallel I/O

74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O

General Description

The F413 is an expandabl e fall-through type high-speed
First-In First-Out (FIFO) buffer memory organized as 64
words by four bits. The 4-bit input and output registers
record and transmit, respectively, asynchronous data in
parallel form. Control pins on the input and ou tput al low f or
handshaking and expa nsion. The 4-bit wide, 62-bit deep
fall-through stack has self-contained control logic.

Features

■ Separate input and output clocks

■ Parallel input and output

■ Expandable without external logic

■ 15 MHz data rate

■ Supply current 160 mA max

■ Available in SOIC, (300 mil only)

Ordering Code:

Order Number Package Number Package Description

74F413PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.

Logic Symbol Connection Diagram

Unit Loading/Fan Out

Pin Names Description

D0–D

O

0–O3

IR Input Ready 1.0/0.667 20 µA/−0.4 mA
SI Shift In 1.0/0.667 20 µA/−0.4 mA
SO Shift Out 1.0/0.667 20 µA/−0.4 mA
OR Output Ready 1.0/0.667 20 µA/−0.4 mA

MR

Data Inputs 1.0/0.667 20 µA/−0.4 mA

3

Data Outputs 50/13.3 −1 mA/8 mA

Master Reset 1.0/0.667 20 µA/−0.4 mA

U.L.

HIGH/LOW

Input I

Output I

IH/IIL
OH/IOL

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Functional Description

Data Input— Data is entered into the FIFO on D0–D

inputs. To enter data the Input Ready (IR) should be HIGH,

74F413

indicating that the first location is ready to accept data.
Data then present at the four data inputs is entered into the
first location when the Shift In (SI) is broug ht HIGH. An SI
HIGH signal causes the IR to go LOW. Data remains at the
first location unti l SI is brought LOW. When SI is brought
LOW and the FIFO is not full, I R will go HIGH, indicating
that more room is available. Simultaneously, data will prop­agate to the second location and continue shifting until it
reaches the output stage or a full location. If the memory is
full, IR will remain LOW.

Data Transfer— Once data is entered into the second cell,
the transfer of any full cell to the adjacen t (downstream)
empty cell is automatic, activated by an on-chip control.
Thus data will stack up at the end of the device while empty

locations will “bubble” to the front. The t

parameter

PT

Block Diagram

defines the time requir ed for the first data to travel from

3

input to the output of a previously empty device.

Data Output— Data is read from the O

When data is shifted to the output stage, Output Ready
(OR) goes HIGH, indicating the presence of valid data.
When the OR is HIGH, data may be shifted out by bringing
the Shift Out (SO) HIGH. A HIGH signal at SO causes the
OR to go LOW. Valid data is maintained while the SO is
HIGH. When SO is brought LOW, the upstream da ta, pro­vided that stage has valid data, is shifted to the output
stage. When new val id data is shif ted to the ou tput stage,
OR goes HIGH. If the FIFO is emptied, OR stays LOW, and

remains as before, i.e., data does not change if

O

0–O3

FIFO is empty.

Input Ready and Outpu t Ready— may also be used as
status signals indicating that the FIFO is completely full
(Input Ready stays LOW for at least t

empty (Output Ready stays LOW for at least t

0–O3

) or completely

PT

).

PT

outputs.

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