Fairchild Semiconductor 74F148CW, 74F148SJX, 74F148SJ, 74F148SCX, 74F148SC Datasheet
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© 1999 Fairchild Semiconductor Corporation DS009480 www.fairchildsemi.com
April 1988
Revised July 1999
74F148 8-Line to 3-Line Priority Encoder
74F148
8-Line to 3-Line Priority Encoder
General Description
The F148 provide s three bits of bina ry code d output representing the position o f the highest order active input, along
with an out p ut i n dic a t ing t he p re s enc e o f an y ac t iv e i nput . I t
is easily expanded via i nput and o utput enable s to p rovi de
priority encoding over many bit s.
Features
■ Encodes eight data lines in priority
■ Provides 3-bit binary priority code
■ Input enable capability
■ Signals when data is present on any input
■ Cascadable for priority encoding of n bits
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Order Number Package Number Package Description
74F148SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F148SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F148PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
EI
I0I1I2I3I4I5I6I7GS A0A1A2EO
HXXXXXXXXHHHHH
LHHHHHHHHH HHH L
LXXXXXXXL LLLLH
LXXXXXXLH L HLL H
LXXXXXLHH L LHLH
LXXXXLHHHL HHLH
LXXXLHHHHLLLHH
LXXLHHHHH LHLHH
LXLHHHHHH L LHH H
LLHHHHHHH LHHH H
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74F148
Unit Loading/Fan Out
Functional Description
The F148 8-input priority e ncoder accept s data from ei ght
active LOW inputs (I
0–I7
) and provides a binary repr esen-
tation on the three active LOW outputs. A priority is
assigned to each input so that when two or more inputs are
simultaneously active , the input with the hig hest priority is
represented on the output, with input line 7 having the highest priority. A HIGH on the Enable Input (EI
) will force all
outputs to the inactive ( HIGH) state an d allow new data to
settle without pr oducing erroneous information at the out-
puts.A Group Signal outp ut (GS
) and Enable Output ( EO)
are provided along with the three priority data outputs (A
2
,
A
1
, A0). GS is active LOW when any input is LOW: this
indicates when any input is active. EO
is active LOW when
all inputs are HIGH. Usi ng the Enable Output along with
the Enable Input allows casc ading for priority en coding on
any number of inp ut signals. Both EO
and GS are in the
inactive HIGH state when the Enable Input is HIGH.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to est im at e propagation delays.
Application
16-Input Priority Encoder
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
I
0
Priority Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
I
1–I7
Priority Inputs (Active LOW) 1.0/2.0 20 µA/−1.2 mA
EI
Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
EO
Enable Output (Active LOW) 50/33.3 −1 mA/20 mA
GS
Group Signal Output (Active LOW) 50/33.3 −1 mA/20 mA
A
0–A2
Address Outputs (Active LOW) 50/33.3 −1 mA/20 mA
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