Fairchild Semiconductor 74ACQ574CW, 74ACQ574SJ, 74ACQ574SCX, 74ACQ574SC, 74ACQ574PC Datasheet
© 1999 Fairchild Semiconductor Corporation DS010634 www.fairchildsemi.com
January 1990
Revised November 1999
74ACQ574 • 74ACTQ574 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs
74ACQ574 • 74ACTQ574
Quiet Series Octal D-Type Flip-Flop
with 3-STATE Outputs
General Description
The ACQ/ACTQ57 4 is a high-speed, low-po wer octal Dtype flip-flop with a buffered Commo n Clock (CP) and a
buffered common Output Enable (OE
). The information
presented to the D inputs is stor ed in the flip-flops on the
LOW-to-HIGH clock (CP) transition.
ACQ/ACTQ574 utilize s FACT Quiet Ser ies technology to
guarantee quiet output switching and improve dynamic
threshold performance . FACT Quiet Series feat ure s GTO
output control and undershoot corrector in addition to a
split ground bus for superior performance.
The ACQ/ACTQ574 is functionally identical to the
ACTQ374 bu t with different pin-out.
Features
■ ICC and IOZ reduced by 5 0%
■ Guaranteed simultaneous switching noise level and
dynamic threshold performan ce
■ Guarante ed pin-to-pin skew AC performance
■ Inputs and outputs on opposite sides of the package
allowing easy interface with microprocessors
■ Functionally identical to the ACQ/ACTQ374
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs source/sink 24 mA
■ Faster prop delays than the standard AC/ACT574
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.
Connection Diagram Pin Descriptions
FACT, Qui et Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACQ574SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACQ574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ574PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACTQ574SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ574PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0–D7
Data Inputs
CP Clock Pulse Input
OE
3-STATE Output Enable Input
O
0–O7
3-STATE Outputs
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74ACQ574 • 74ACTQ574
Logic Symbols
IEEE/IEC
Functional Description
The ACQ/ACTQ574 consists of eight edge-trigger ed flipflops with individual D- type inputs and 3-STATE true outputs. The buffered clock a nd buffered Output Enable a re
common to all flip-flops. The eight flip-flops will sto re the
state of their individ ual D-type inputs that mee t the setup
and hold time requirements on the LOW-to-HIGH Clock
(CP) transition. With the Output Enable (OE
) LOW, the
contents of the eight flip-flops are avai lable at th e outputs.
When OE
is HIGH, the out puts go to the high impedance
state. Operation of the OE
input does not affect the state of
the flip-flops.
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Internal Outputs
Function
OE CP D Q O
N
H H L NC Z Hold
HHH NC Z Hold
H
LL ZLoad
H
HH ZLoad
L
L L L Data Available
L
H H H Data Available
L H L NC NC No Change in Data
L H H NC NC No Change in Data
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74ACQ574 • 74ACTQ574
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute max imum ratings are those values beyond which da m age
to the device may occu r. The databook spe cificatio ns shou ld be met, wit hout exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside datab ook s pecifications.
DC Electrical Characteristics for ACQ
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output S ource
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
DC Latch-Up Source or
Sink Current ±300 mA
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
)
ACQ 2.0V to 6.0V
ACTQ 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate ∆V/∆t
ACQ Devices
V
IN
from 30% to 70% of V
CC
VCC @ 3.0V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate ∆V/∆t
ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
TA = +25°CT
A
= −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
= −50 µA
5.5 5.49 5.4 5.4
VIN = VIL or V
IH
3.0 2.56 2.46 IOH = −12 mA
4.5 3.86 3.76 V I
OH
= −24 mA
5.5 4.86 4.76 I
OH
= −24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
5.5 0.001 0.1 0.1
VIN = VIL or V
IH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
I
IN
Maximum Input
5.5 ±0.1 ±1.0 µAVI = VCC, GND
(Note 4) Leakage Current
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5 4.0 40.0 µA
VIN = V
CC
(Note 4) Supply Current or GND
I
OZ
Maximum 3-STATE VI (OE) = VIL, V
IH
Leakage Current 5.5 ±0.25 ±2.5 µAVI = VCC, GND
VO = VCC, GND
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