Fairchild Semiconductor 74ACQ544SCX, 74ACQ544SC, 74ACQ544CW, 74ACQ544SPC Datasheet
© 2000 Fairchild Semiconductor Corporation DS010685 www.fairchildsemi.com
March 1990
Revised September 2000
74ACQ544 • 74ACTQ544 Quiet Series
Octal Registered Transceiver with 3-STATE Outputs
74ACQ544 • 74ACTQ544
Quiet Series
Octal Registered Transceiver
with 3-STATE Outputs
General Description
The ACQ/ACTQ544 is an inverting octal transceiver containing two sets of D-type registers for temporary storage of
data flowing in eit her dir ectio n. S e par ate La tch Enable and
Output Enable inputs are provid ed for each register to pe rmit independent i nput a nd ou tput co ntrol in eit her d irecti on
of data flow. The 544 inverts data in both directions.
The ACQ/ACTQ utilizes Fairchild FACT Quiet Series
technology to guarantee quiet output switching and
improved dynamic threshold performance. FACT Quiet
Series features GTO
output control and undersho ot cor-
rector in addition to a sp lit ground bus for supe rior performance.
Features
■ Guaranteed simultaneous switching noise level and
dynamic threshold performan ce
■ Guarante ed pin-to-pin ske w AC performance
■ 8-bit inverting octal latched transceiver
■ Separate controls for data flow in each direction
■ Back-to-back registers for storage
■ Outputs source/sink 24 mA
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Connection Diagram Pin Descriptions
FACT, Qui et Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACQ544SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ544SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ544SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ544SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
CEAB
A-to-B Enable Input (Active LOW)
CEBA
B-to-A Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input (Active LOW)
LEBA
B-to-A Latch Enable Input (Active LOW)
A
0
–A
7
A-to-B Data Inputs or
B-to-A 3-STA TE Outputs
B
0
–B
7
B-to-A Data Inputs or
A-to-B 3-STA TE Outputs
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74ACQ544 • 74ACTQ544
Logic Symbols
IEEE/IEC
Functional Description
The ACQ/ACTQ544 contains two sets of eight D-type
latches, with separate input and output controls fo r each
set. For data flow from A to B, for example, the A-to-B
Enable (CEAB
) input must be LOW in order to enter data
from A
0
–A7 or take data from B0 –B7, as indicated in the
Data I/O Control Table. With CEAB
LOW, a LOW signal on
the A-to-B Latch Enable (LEAB
) input makes the A-to-B
latches transparent; a sub seq uen t L OW-to-HI GH tr an sition
of the LEAB
signal puts the A latches in the storag e mode
and their outputs no longer ch ange with the A inputs. With
CEAB
and OEAB both LOW, the 3-STATE B output buffers
are active and reflect the data present at the output of the A
latches. Control of data flow from B to A is similar, but using
the CEBA
, LEBA and OEBA inputs.
Data I/O Control Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA
, LEBA and OEBA
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Latch Output
CEAB
LEAB OEAB Status Buffers
H X X Latched High Z
XHXLatched —
L L X Transparent —
XXH — High Z
LXL — Driving
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74ACQ544 • 74ACTQ544
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute max imum ratings are t hose values bey ond which damage
to the device may occu r. The databook spe cificatio ns shou ld be met, wit hout exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside da t ab ook specifications.
DC Electrical Characteristics for ACQ
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output S ource
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
DC Latch-up Source or
Sink Current ±300 mA
Junction Temperature (T
J
)
PDIP 140
°C
Supply Voltage V
CC
ACQ 2.0V to 6.0V
ACTQ 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate
∆V/∆t
ACQ Devices
V
IN
from 30% to 70% of V
CC
VCC @3.0V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate
∆V/∆t
ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
TA = + 25°CTA = − 40°C to + 85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
= − 50 µA
5.5 5.49 5.4 5.4
V
IN
= VIL or V
IH
3.0 2.56 2.46 IOH = − 12 mA
4.5 3.86 3.76 V IOH = − 24 mA
5.5 4.86 4.76 IOH = − 24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
5.5 0.001 0.1 0.1
VIN = VIL or V
IH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
I
IN
Maximum Input 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND
(Note 4) Leakage Current
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
ICC (Note 4) Maximum Quiescent Supply Current 5.5 8.0 80.0 µAVIN= VCC or GND
I
OZT
Maximum I/O VI (OE) = VIL, V
IH
Leakage Current 5.5 ±0.6 ±6.0 µAVI = VCC, GND
VO = VCC, GND
V
OLP
Quiet Output
5.0 1.1 1.5 V
Figures 1, 2
Maximum Dynamic V
OL
(Note 5)(Note 6)
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