The FAN7318 is a LCD backlight inverter drive IC that
controls P-N half-bridge topology.
The FAN7318 provides a low-cost solution and reduces
external components by integrating proprietary wave
rectifiers for open-lamp protection and regulation. The
operating voltage range of the FAN7318 is wide, so an
external regulator isn’t necessary to supply the voltage to
the IC.
The FAN7318 provides various protections, such as
open-lamp regulation, open-lamp protection, short-Lamp
protection, CMP-high protection, and FB-high protection,
to increase the system reliability. The FAN7318 provides
burst dimming and analog dimming.
1 TIMER This pin is for protection delay time setting.
2 CMP
3 ADIM This pin is the input for negative analog dimming.
4 CT
5 REF
6 BCT
7 BDIM
8 ENA This pin is for turning on/off the IC.
9 GND This pin is the ground.
10 OUTB This pin is NMOS gate-drive output.
11 OUTA This pin is PMOS gate-drive output.
12 VIN This pin is the supply voltage of the IC.
13 OLR4 This pin is for open-lamp regulation. Its functions are the same as the OLR1 pin.
14 OLP4
15 OLR3 This pin is for open-lamp regulation. Its functions are the same as the OLR1 pin.
16 OLP3
17 OLR2 This pin is for open-lamp regulation. Its functions are the same as the OLR1 pin.
18 OLP2
19 OLR1
20 OLP1
Error amplifier output. Typically, a compensation capacitor is connected to this pin from the
ground.
This pin is for programming the switching frequency. Typically, a capacitor is connected to
this pin from ground and a resistor is connected to this pin from the REF pin.
This pin is 5V reference output. Typically, resistors are connected to this pin from the CT pin
and the BCT pin.
This pin is for programming the frequency of the burst dimming. Typically, a capacitor is
connected to this pin from ground and a resistor is connected to this pin from the REF pin.
This pin is the input for negative burst dimming. The voltage range of 0.5 to 2V at this pin
controls burst mode duty cycle from 0% to 100%.
This pin is for open-lamp protection and feedback control of lamp currents. Its functions are
the same as the OLP1 pin.
This pin is for open-lamp protection and feedback control of lamp currents. Its functions are
the same as the OLP1 pin.
This pin is for open-lamp protection and feedback control of lamp currents. Its functions are
the same as the OLP1 pin.
This pin is for open-lamp regulation and short-lamp protection. It has the same functions as
other OLR pins and is connected to the full-wave rectifier internally. When the maximum of
rectified OLR inputs is between 1.34V and 2V, the error amplifier output current is limited to
3.2µA; and when the maximum of rectified OLR inputs reaches 2V, the error amplifier output
current is 0A and its output voltage maintains constant. The maximum of rectified OLR
inputs is inputted to the negative of another error amplifier for feedback control of lamp
voltage. When the maximum of rectified OLR inputs is more than 2.2V, another error
amplifier for OLR is operating and lamp voltage is regulated. In normal mode, if the
maximum of rectified OLR inputs is higher than 1.35V or if the minimum of rectified OLR
inputs is lower than 0.3V for a predetermined time by the TIMER pin capacitor and a internal
current source 50µA, the IC shuts down to protect the system in over-voltage condition,
short-lamp condition, respectively.
This pin is for open-lamp protection and feedback control of lamp currents. It has the same
functions as other OLP pins and is connected to the half-wave rectifier and the full-wave
rectifier internally. In striking mode, if the minimum of rectified OLP inputs is less than 0.7V
for a predetermined time by the TIMER pin capacitor and an internal current source or, in
normal mode, if the minimum of rectified OLP inputs is less than 0.5V for another
predetermined time by the TIMER pin capacitor and another internal current source; the IC
shuts down to protect the system in open-lamp condition. The maximum of rectified OLP
inputs is inputted to the negative of the error amplifier for feedback control of lamp current.
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
VIN IC Supply Voltage 6 30 V
TA Operating Temperature Range -25 +85
TJ Operating Junction Temperature +150
T
Storage Temperature Range -65 +150
STG
θJA Thermal Resistance Junction-Air
PD Power Dissipation 1.4 W
Notes:
1. Thermal resistance test board; size: 76.2mm x 114.3mm x 1.6mm (1S0P); JEDEC standard: JESD51-2, JESD51-3.
For typical values, TA=25°C, VIN=15V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to -25°C ~
85°C are guaranteed by design based on final characterization results.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
Under-Voltage Lockout Section (UVLO)
Vth Start Threshold Voltage Increase VIN 4.9 5.2 5.5 V
V
Start Threshold Voltage Hysteresis Decrease VIN 0.20 0.45 0.60 V
thhys
Ist Startup Current VIN=4.5V 10 70 100 µA
Iop Operating Supply Current VIN=15V, Not Switching 0.5 2.0 3.5 mA
For typical values, TA=25°C, VIN=15V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to -25°C ~
85°C are guaranteed by design based on final characterization results.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
Analog Dimming Section
ADIM=0V, T
ADIM=0V 1.212 1.310 1.408
AV
Reference Voltage
rexx
ADIM=0.5V 1.16
ADIM=1.0V 0.99
Error Amplifier Section
l
Output Sink Current OLP=2.5V, ADIM=2.5V 63 76 94 µA
sin
l
Output Source Current 1 OLP=0V, ADIM=0V -65 -50 -35 µA
sur1
l
Output Source Current 2 CMP=3V -1.7 -1.3 -0.9 µA
sur2
I
Burst CMP Sink Current BDIM=5V, BCT=0V 41 52 63 µA
bsin
I
OLP Input Current
olpi
I
OLP Output Current OLP=-2V -30 -20 -10 µA
olpo
OLP=2V 0 µA
OLP=0.3V 0.31 V
V
Rectifiers Output of OLP
lpfx
V
OLP Input Voltage Range
olpr
(3)
-4 4 V
OLP=1.5V 1.5 V
Open-Lamp Regulation Section
I
G
olr1
I
olr2
V
olr1
V
olr2
V
olr3
mOLR
I
ors
I
olri
I
olro
V
olrr
Error Amplifier Source Current for
Open-Lamp Regulation
OLR Sweep 0 µA
Open-Lamp Regulation Voltage 1 OLR Sweep 1.24 1.34 1.44 V
Open-Lamp Regulation Voltage 2 Striking, OLR Sweep 1.88 1.98 2.08 V
For typical values, TA=25°C, VIN=15V, and -25°C ≤ TA ≤ 85°C, unless otherwise specified. Specifications to -25°C ~
85°C are guaranteed by design based on final characterization results.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
Protection Section
V
Open-Lamp Protection Voltage 0
olp0
V
Open-Lamp Protection Voltage 1 Sweep OLP 0.42 0.49 0.56 V
olp1
V
CMP-High Protection Voltage Sweep CMP 3.4 3.5 3.6 V
cmpr
V
High-FB Protection Voltage
hfbp
V
Short-Lamp Protection Voltage Sweep TIMER 0.22 0.30 0.38 V
slp
V
Timer Threshold Voltage 1 Striking, Sweep TIMER 2.87 3.02 3.17 V
tmr1
V
Timer Threshold Voltage 2 Sweep TIMER 1.0 1.1 1.2 V
tmr2
I
Timer Current 1 OLP=0V 1.7 2.1 2.5 µA
tmr1
I
Timer Current 2 OLR=1.8V 40 50 60 µA
tmr2
TSD Thermal Shutdown
V
Over-Voltage Protection Voltage Sweep OLR 1.24 1.34 1.44 V
ovp
dcr
ENA2.3V OLP Disable/Enable Change
Voltage
(4)
150 °C
Output Section
V
PMOS Gate High Voltage
pdhv
V
PMOS Gate Low Voltage VIN=15V VIN-9.5 VIN-8.5 VIN-7.0 V
phlv
V
NMOS Gate High Voltage VIN=15V 8.0 9.0 10.5 V
ndhv
V
NMOS Gate Low Voltage
ndlv
V
V
I
pdsur
I
pdsin
I
ndsur
I
ndsin
puv
nuv
PMOS Gate Voltage with UVLO
Activated
NMOS Gate Voltage with UVLO
Activated
PMOS Gate Drive Source Current
PMOS Gate Drive Sink Current
NMOS Gate Drive Source Current
NMOS Gate Drive Sink Current
(4)
Maximum / Minimum Duty Cycle
DC
Minimum Duty Cycle
MIN
DC
Maximum Duty Cycle
MAX
(4)
f
(4)
f
Note:
4. These Parameters, although guaranteed, are not 100% tested in production.