Fairchild (Now ON) BSS84, BSS84 Schematic [ru]

February 2013

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BSS84
P-Channel Enhancement Mode Field-Effect Transistor

BSS84 — P-Channel Enhancement Mode Field-Effect Transistor

Features

 -0.13 A, -50 V, R

= 10 Ω at VGS = -5 V

DS(ON)

 Voltage-Controlled P-Channel Small-Signal

Switch

 High-Density Cell Design for Low R
 High Saturation Current

D

DS(ON)

D

Description

This P-channel enhancement-mode field-effect
transistor is produced using Fairchild’s proprietary,
high cell density, DMOS technology. This very high
density process minimizes on-state resistance and to
provide rugged and reliable performance and fast
switching. The BSS84 can be used, with a minimum
of effort, in most applications requiring up to 0.13 A
DC and can deliver current up to 0.52 A. This product
is particularly suited to low-voltage applications
requiring a low-current high-side switch.

S

SOT-23

G

SG

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommende d.
In addition, extended exposure to stresses above the reco mm end ed oper ating c on dition s ma y affect de vice relia bil it y.
The absolute maximum ratings are stress ratings only. Values are at T

Symbol

V

Drain-Source Voltage

DSS

V

Gate-Source Voltage

GSS

ID Drain Current

PD

TJ, T

Maximum Power Dissipation
Derate Above 25°C

Operating and Storage Junction Temperature Range

STG

Maximum Lead Temperature for Soldering

TL

Purposes, 1/16” from Case for 10 Seconds

(1)

Parameter Ratings Unit

Continuous
Pulsed

(1)

0.36

= 25°C unless otherwise noted.

A

−50
±20

−0.13

−0.52

2.9

−55 to +150 °C
300

V
V
A
A

W

mW / °C

°C

Thermal Characteristics

R

θJA

Thermal Resistance, Junction-to-Ambient

350

°C/W

Note:

1. R

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference

θJA

is defined as the solder mounting surface of the drain pins. R

is guaranteed by design, while R

θJA

θJA

is

determined by the user's board design.

a) 350°C/W when mounted on a minimum pad

Scale 1: 1 on letter-size paper.

Package Marking and Ordering Information

Device Marking Device Reel Size Tape width Quantity

SP BSS84 7’’ 8mm 3000

© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
BSS84 • Rev. 1.1.0

μ

)

)

)

)

g

g

BSS84 — P-Channel Enhancement Mode Field-Effect Transistor

Electrical Characteristics

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Symbol Parameter Conditions Min. Typ. Max. Unit

Off Characteristics

BV

Drain–Source Breakdown Voltage

DSS

ΔBV

I

DSS

Breakdown Voltage Temperature

DSS

Coefficient

ΔTJ

Zero Gate Voltage Drain Current

V

= 0 V, ID = –250 μA

GS

I

= –250 μA,

D

Referenced to 25℃

= –50 V, VGS = 0 V –15

V

DS

VDS = –50 V, VGS = 0 V,
TJ = 125°C

I

Gate–Body Leakage.

GSS

BV

Drain–Source Breakdown Voltage

DSS

On Characteristics

V

Gate Threshold Voltage VDS = VGS, ID = –1 mA –0.8 –1.7 –2 V

GS(th

V

GS(TH)

R

DS(on)

I

D(on

Gate Threshold Voltage
Temperature Coefficient

T

J

Static Drain–Source
On–Resistance

On–State Drain Current VGS = –5 V, VDS = – 10 V –0.6 A

(2)

V

= ±20 V, VDS = 0 V

GS

V

= 0 V, ID = –250 μA

GS

I

= –1 mA,

D

Referenced to 25℃

= –5 V, ID = –0.10 A

V

GS

V

= –5 V, ID = –0.10 A,

GS

T

= 125°C

J

–50 V

–48

mV / ℃

A

–60

±10

μA

nA

–50 V

3

1.2 10.0

1.9 17.0

mV / ℃

Ω
Ω

gFS Forward Transconductance VDS = –25 V, ID = – 0.10 A 0.05 0.60 S

Dynamic Characteristics

C

Input Capacitance

ISS

C

Output Capacitance 10 pF

OSS

C

Reverse Transfer Capacitance 5 pF

RSS

V

= –25 V,

DS

= 0 V,

V

GS

f = 1.0 MHz

RG Gate Resistance VGS = –15 mV, f = 1.0 MHz 9

Switching Characteristics

t

Turn–On Delay

d(on

tr Turn–On Rise Time 6.3 13.0 ns

t

Turn–Off Delay 10 20 ns

d(off

(2)

= –30 V, ID = – 0.27 A,

V

DD

= –10 V, R

V

GS

GEN

= 6 

73 pF

Ω

2.5 5.0 ns

tf Turn–Off Fall Time 4.8 9.6 ns

Qg Total Gate Charge

Q

Gate–Source Charge 0.2 nC

s

Q

Gate–Drain Charge 0.3 nC

d

V

= –25 V, ID = –0.10 A,

DS

V

= –5 V

GS

0.9 1.3 nC

Drain-Source Diode Characteristics and Maximum Ratings

IS Maximum Continuous Drain-Source Diode Forward Current -0.13 A

VSD

tRR Diode Reverse-Recovery Time

QRR Diode Rev erse-Recovery Charge 3 nC

Drain-Source Diode Forward
Voltage

VGS = 0 V, IS = - 0.26 A
I

= -0.1 A,

F

/ dt = 100 A / µs

d

iF

Note:

2. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2.0%.

(2)

-0.8 -1.2 V
10 ns

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© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
BSS84 • Rev. 1.1.0 2

Typical Characteristics

BSS84 — P-Channel Enhancement Mode Field-Effect Transistor

1

V

= -5V -4.5V

GS

0.8

0.6

0.4

, DRAIN CURRENT (A)

D

-I

0.2

0

012345

-V

DS

-3.5V

-3.0V

-2.5V

, DRAIN TO SOURCE VOLTAGE (V)

2

1.8
VGS=-3.0V

1.6

1.4

, NORMALIZED

1.2

DS(ON)

R

1

DRAIN-SOURCE ON-RESISTANCE

0.8

0 0.2 0.4 0.6 0.8 1

-3.5V

-4.0V

-I

, DRAIN CURRENT (A)

D

-4.5V

Figure 1. On-Region Characteristics Figure 2. On-Resistance Variation with Drain

Current and Gate Voltage

1.8
ID = -0.10A

1.6

1.4

1.2

, NORMALIZED

DS(ON)

0.8

R

0.6

DRAIN-SOURCE ON-RESISTANCE

0.4

= -5V

V

GS

1

-50 -25 0 25 50 75 100 125 150

T

, JUNCTION TEMPERATURE (oC)

J

5

4

3

, ON-RESISTANCE (OHM)

2

DS(ON)

R

TA = 25oC

1

22.533.544.55

TA = 125oC

-V

, GATE TO SOURCE VOLTAGE (V)

GS

-5.0V

ID = -0.05A

Figure 3. On-Resistance Variation with

Temperature

1

VDS = -5V

0.8

0.6

0.4

, DRAIN CURRENT (A)

D

-I

0.2

0

1 1.5 2 2.5 3 3.5 4

, GATE TO SOURCE VOLTAGE (V)

-V

GS

TA = -55oC

Figure 5. Transfer Characteristics Figure 6. Body Diode Forward Voltage Variation with

125oC

25oC

Figure 4. On-Resistance Variation with Gate-to-

Source Voltage

1

VGS = 0V

0.1

0.01

0.001

, REVERSE DRAIN CURRENT (A)

S

-I

0.0001

0.0 0.2 0.4 0.6 0.8 1.0 1.2

TA = 125oC

25oC

BODY DIODE FORWARD VOLTAGE (V)

-V

SD,

-55oC

Source Current and Temperature

© 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com
BSS84 • Rev. 1.1.0 3