Fairchild USB1T1105A service manual

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USB1T1105A
Universal Serial Bus Peripheral Transceiver

with Voltage Regulator

USB1T1105A Universal Serial Bus Peripheral Transceiver with Voltage Regulator

January 2005
Revised August 2005

General Description

The USB1T1105A is an Universal Serial Bus Specification Rev

2.0 compliant transceiver. The device provides an USB inter­face for Full-Speed (12Mbit/s) USB applications. The
USB1T1105A provides excellent flexibility, allowing differential
and single ended inputs while an integrated voltage regulator
sets the I/O level to 1.65V to 3.6V . Utilizing an integrated 5.0V to

3.3V voltage regulator, the part can be powered directly from
the USB host (V
local sources while used in devices with low supply voltages.

The USB1T1105A provides 15kV ESD protection on the USB
bus pins (D
devices while providing excellent protection to larger and more
expensive ASICs and USB controllers.

/D

) to minimize the power consumed from the

BUS

). This eliminates the need for any external ESD

Features

O

Complies with Universal Serial Bus Specification 2.0

O

Integrated 5V to 3.3V voltage regulator for powering VBus

O

Utilizes digital inputs and outputs to transmit and receive
USB cable data

O

Supports full speed 12Mbits/s speed data rates

O

Ideal for portable electronic devices

O

15kV contact HBM ESD protection on bus pins

O

3.3mm leadless package

O

Industry standard HBCC footprint is lead-free

Applications

O

Cell phone

O

PDA

O

Digital camera

O

MP3

Ordering Code:

Order Number

USB1T1105AMHX MLP16HB Pb-Free 16-T erminal Molded Leadless Package (MHBCC), JEDEC MO-217, 3mm Square

Package

Number

Package Description

Pb-Free package per JEDEC J-STD-020B.

Logic Diagram

© 2005 Fairchild Semiconductor Corporation DS500911 www.fairchildsemi.com

Connection Diagram

USB1T1105A

Terminal Descriptions

(Bottom View)

Terminal

Number

Terminal

Name

I/O T erminal Description

1OEI Output Enable: Active LOW enables the transceiver to transmit data on the bus. When

not active the transceiver is in the receive mode (CMOS level is relative to V

2 RCV O Receive Data Output: Non-inverted CMOS level output for USB differential Input (CMOS

3V

4V

p

m

output level is relative to V
RCV output is stable and preserved during SE0 condition.

O Single-ended D receiver output VP (CMOS level relative to V

Used for external detection of SEO, err or conditions, speed of connected device;
Driven HIGH when no supply connected to V

O Single-ended D receiver output Vm (CMOS level relative to V

). Driven LOW when SUSPN is HIGH;

CCIO

CC

and V

REG

.

CCIO

CCIO

):

):
Used for external detection of SEO, err or conditions, speed of connected device;
Driven HIGH when no supply connected to V

CC

and V

REG

.

5 SUSPND I Suspend:

Enables a low power state (CMOS level is relative to V
active (HIGH) it will drive the RCV pin to logic “0” state.

6 MODE I MODE input (CMOS level is relative to V

MODE (V

, Vmo) whereas a LOW enables the single-ended MODE (Vo, V

po

). A HIGH selects the differential input

CCIO

). While the SUSPND pin is

CCIO

FSEO

Table 2 and Table 3

7V

CCIO

Supply Voltage for digital I/O pins (1.65V to 3.6V):
When not connected the D
independent of V

CC



and D pins are in 3-STATE. This supply bus is totally

(5V) and V

REG

(3.3V).

8NCNC

10, 9 D

11 V

12 V

13 V



, D



/ V

po

o

/ F

mo

SEO

(3.3V) Internal Regulator Option:

REG

AI/O Data , Data : Differential data bus conforming to the USB standard.

I Driver Data Input (CMOS level is relative to V

see Table 2 and Table 3

I Driver Data Input (CMOS level is relative to V

see Table 2 and Table 3

); Schmitt trigger input;

CCIO

); Schmitt trigger input;

CCIO

Regulated supply output voltage (3.0V to 3.6V) during 5V operation;

14 V

decoupling capacitor of at least 0.1

(5.0V) Internal Regulator Option:

CC

P

F is required.

Used as supply voltage input (4.0V to 5.5V); can be connected directly to USB line
Vbus.

CCIO

)

) see

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USB1T1105A

Terminal

Number

15 V

16 Config I USB connect or disconnect software control input.

Exposed

Diepad

Terminal

Name

(3.3V) Pull-up Supply Voltage (3.3V r 10%):

PU

GND GND GND supply down bonded to exposed diepad to be connected to the PCB GND.

I/O T erminal Description

:

Connect an external 1.5k
Pin function is controlled by Config input pin:
Config = LOW
Config = HIGH

Configures 3.3V to external 1.5k



VPU (3.3V) is floating (High Impedance) for zero pull-up current.



VPU (3.3V) = 3.3V; internally connected to V

resistor on D (FS data rate);

:

resistor on D when HIGH.

Functional Description

The USB1T1105A transceiver is designed to convert CMOS
data into USB differential bus signal levels and to convert USB
differential bus signal to CMOS data.

To minimize EMI and noise the out puts are edge rate controlled
with the rise and fall times controlled and defined for full speed
data rates. The rise, fall times are balanced between the differ­ential pins to minimize skew.

Table 1 describes the specific pin functionality selection. Table
2, Table 3, and Table 4 describe the specific Truth Tables for
Driver and Receiver operating functions.

The USB1T1105A also has the capability of various power sup­ply configurations to support mixed voltage supply applications
(see Table 5) and Power S upply Configurations and Options for
detailed descriptions.

Functional Tables

TABLE 1. Function Select

SUSPND OE D, D RCV

L L Driving &

Receiving

L H Receiving

(Note 1)

H L Driving Inactive

HH3-STATE

(Note 1)

Active Active Normal Driving

Active Active Receiving

(Note 2)

Inactive

(Note 2)

V

p/Vm

(Differential Receiver Active)

Active Driving during Suspend

Active Low Power State

(Differential Receiver Inactive)

REG

Function

(3.3V).

Note 1: Signal levels is function of connection and/or pull-up/pull-down resistors.
Note 2: For SUSPND = HIGH mode the differential receiver is inactive and the output RCV output is forced LOW. The out-of-suspend signaling (K) is detected via the single-

ended receiver outputs of the Vp and Vm pins.

TABLE 2. Driv e r Func tion (OE = L) using Differential Input Interface Mode Pin = H

V

mo

L L SE0 (Note 3)
L H Differential Logic 1
H L Differential Logic 0
H H Illegal State

Note 3: SE0 = Single Ended Zero

TABLE 3. Driver Function (OE = L) using Single-ended Input Interface Mode Pin = L

FSE0

L L Differential Logic 0
L H Differential Logic 1
H L SE0 (Note 4)
H H SE0 (Note 4)

V

po

V

o

3 www.fairchildsemi.com

Data

Data

Note 4: SE0 = Single Ended Zero

TABLE 4. Receiver Function (OE = H)

D, D RCV

USB1T1105A

X = Don’t Care

Differential Logic 1 H H L
Differential Logic 0 L L H

SE0 X L L

Sharing Mode L H H

Power Supply Configurations and Options

The three modes of power supply operation are:

• Normal Mode: Regulated Output and Regulator Bypass

1. Regulated Output: V
connected to 5V (4.0V to 5.5V) and the internal voltage
regulator then produces 3.3V for the USB connections.

2. Internal Regulator Bypass Mode: V
both V

(5.5) and V

CC

source (3.0V to 3.6V).

In both cases for normal mode the V
voltage source (1.65V to 3.6V) that is a function of the exter­nal circuit configuration.

• Sharing Mode: V
V

are not connected. In this mode the D and D pins are

REG

CCIO

is connected and VCC (5.0) is

CCIO

is connected and

(3.3) are connected to a 3.3V

REG

CCIO

is an independent

CCIO

is only supply connected. VCC and

V

p

V

m

3-STATE and the USB1T1105A allows external signals up to

3.6V to share the D
limits leakage from D

such that device is in low power (suspended) state.

V

CCIO



and D bus lines. Internally the circuitry



and D pins (maximum 10 PA) and

Terminals Vbusmon and RCV are forced LOW as an indica­tion of this mode with Vbusmon being ignored during this
state.

• Disable Mode: V
V

and V

CC



D

REG

are 3-STATE and VPU is HIGH Impedance (switch is

is not connected. VCC is connected, or

CCIO

are connected. 0V to 3.3V in this mode D and

turned off). The USB1T1105A allows external signals up to

3.6V to share the D
limits leakage from D



and D bus lines. Internally the circuitry



and D terminals (maximum 10PA).

A summary of the Supply Configurations is described in Table 5.

Pins

V

CC

(5V)

(3.3V) Pulled LOW

V

REG

V

CCIO

V

(3.3V) 3-STATE (Off) 3-STATE (Off) 3.3V Available if

PU

D



, D



, V

V

p

m

RCV L Invalid Function of Mode Set Up Function of Mode Set Up

OE, SUSPND,
Config, V

V

mo/FSEO

Note 5: Hi-Z or forced LOW.

po/Vo

, MODE

,

TABLE 5. Power Supply Configuration Options

Power Supply Mode Configuration

Sharing Disable



3.6V Connected

Normal

(Regulated Output)

Connected to 5V Source Connected to V

to 5V Source

Regulator OFF

3.3V, 300 PA

Regulated Output

3.3V, 300 PA

Regulated Output

1.65V to 3.6V Source Not Connected 1.65V to 3.6V Source 1.65V to 3.6V Source

Config = HIGH

3-STATE 3-STATE Function of Mode Set Up Function of Mode Set Up

H Invalid Function of Mode Set Up Function of Mode Set Up

Hi-Z Hi-Z Function of Mode Set Up

Normal

(Regulator Bypass)

(3.3V)

[max drop of 0.3V]

(2.7V to 3.6V)

to 3.3V Source

3.3V Available if
Config = HIGH

REG

Connected

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