Fairchild UniFET service manual
www.fairchildsemi.com
AN-9066
UniFET™ — Optimized Switch for Discontinuous Current
Mode Power Factor Correction
Abstract
This application note discusses merits of planar technology
power MOSFET in discontinuous current mode power
factor correction application. In most test conditions it is
cost competitive and gives performance benefits compared
to a super-junction technology device. The benefits are
verified through the mathematical simulation and systemlevel experiments. A new planar technology power
MOSFET from Fairchild shows faster switching
characteristics that contribute to higher efficiency and lower
device temperature.
Introduction
Switch-mode power supplies are increasingly being
designed with an active power factor correction at the input
stage to meet international regulations for harmonics. The
boost topology in discontinuous current mode (DCM) is
most suitable power factor correction (PFC) method for
converters with less than 300W power rating[1]. In this
topology, the switching-on power loss of boost switch is
negligible, and the major power losses are the switching-off
losses and conduction losses. After the super-junction
devices have been introduced, they are often considered as
optimized switches for active power factor correction
because of extremely low on-resistance and highly nonlinear capacitance curves. In the discontinuous current mode
power factor correction, however, the conventional planar
devices can compete against the powerful super-junction
family. This article shows that Fairchild’s UniFET™ power
MOSFET can provide performance superior to the superjunction devices in the discontinuous current mode power
factor correction applications.
Power MOSFET Technologies
The super-junction technology utilizes deep P-type pillar
structure in the body of the power MOSFET. The effect of
the pillars is to confine the electric field in the lightly doped
epitaxial region of the power MOSFET. Thanks to this Ppillar, the resistivity of N-epi can be reduced compared to
the conventional planar technology, while maintaining the
same breakdown voltage. Therefore, typical on-resistance of
the super-junction MOSFETs is only one third of the
conventional planar power MOSFETs at the same chip size.
Most commercially available super-junction devices adopt
multiple epi-layers to build the deep P-pillar structure. The
multi-epi process, however, has some disadvantages, such
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.1 • 4/3/09
as increased process steps and higher manufacturing cost. In
contrast, the UniFET™ power MOSFET utilizes a planar
double-diffused metal-oxide semiconductor (DMOS)
process that is very mature and highly cost competitive.
Moreover, it has improved ring terminations and optimized
active cell structures compared to the conventional planar
power MOSFETs. The resulting specific on-resistance of
the UniFET is even close to some super-junction devices at
500V of breakdown voltage range.
The planar power MOSFETs also have higher reliability
than the super-junction MOSFETs under unclamped
inductive switching (UIS) condition, which can occur
during power supply power-up or AC line transient. The
devices can enter breakdown, and even be destroyed, in the
worst situations. Typically, the planar MOSFETs are much
better than the super-junction devices in UIS mode. The
newest super-junction technology enabled equivalent UIS
rating to the planar MOSFETs at unit area; however, its
practical rating as a single device is still inferior to planar
MOSFETs because of smaller die size. The UIS ruggedness
of UniFET is also far better than previous generations of
planar technology. For an example, a 265mΩ, 500V
UniFET shows more than 80A of avalanche current under
low coil UIS test. Moreover, it does not fail at all in the test.
On the contrary, a conventional planar MOSFET with same
on-resistance failed at around 40A. The improved
ruggedness ensures enhanced reliability. In terms of
switching performance, a gate charge is one of the
benchmarks to compare different devices. The UniFET has
a smaller gate charge, faster switching characteristics, and
reduced switching power losses than the conventional
planar MOSFETs. Some typical electric characteristics
benchmarks are shown in
Table 1. Gate Charge and Parasitic Capacitance
Benchmark Data
Q
FDB12N50 22nC 140pF 985Pf 12pF
FQB12N50 39nC 220pF 1550pF 25pF
FDA16N50 32nC 235pF 1495pF 20pF
FQA16N50 60nC 325pF 2300pF 35pF
Note:
1. FDB12N50 and FDA16N50 are UniFET™. FQB12N50
and FQA16N50 are QFET
planar power MOSFET.
Table 1.
G
C
OSS
®
, is a previous generation of
C
ISS
C
RSS
AN-9066 APPLICATION NOTE
Discontinuous Current Mode Power
Factor Correction
Generally, power factor correction circuits have used a
boost topology because it is simple and low costs. There are
two modes of the power factor correction boost circuit
operation. One is continuous current mode (CCM) that has
continuous inductor current. This mode has many benefits,
like lower core loss and ripple current and a smaller input
filter; but it requires very fast reverse recovery diode as the
boost diode since the boost switch in being switched on
while the inductor current is not zero. The discontinuous
current mode switches on the boost switch when the
inductor current is zero, allowing less expensive diodes to
be used. The turn-on loss of the boost switch is also
negligible. Usually, the discontinuous current mode is used
for small power supplies, 300W or less, that have relatively
small inductor current, but are very sensitive to cost
constraints.
450
Simulation and Experimental
Results
Conduction loss is easy to evaluate because the R
is clearly stated in datasheets, but the switching loss varies
greatly by the circuit conditions. To compare the switching
performance in the system, one UniFET and one superjunction device are selected and evaluated. An inductive
switching test board was used to measure switching loss at
turn-off transient. In this way, it is possible to keep the
important test variables, like drain current and external
series gate resistor, under control.
Figure 1 shows the energy loss curves with different
conditions of the series gate resistor and the drain-current.
The solid traces indicate the losses of the UniFET and the
dotted traces are losses of the super-junction device. There
are four different lines per device, according to the pre-set
drain current levels. The drain current levels are 20A, 10A,
6.5A, and 1.8A from top to bottom.
DS(on)
value
400
350
300
250
200
150
100
S wit c hin g- o ffE n er g yLos s [ µJ ]
50
0
4 8 12 16 20 24
External Series Gate Resistance [Ω]
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.1 • 4/3/09 2
450
400
350
300
250
200
150
100
Switching-Off Enery Loss [µJ]
50
0
4 8 12 16 20 24
External Series Gate Resistance[Ω]
Figure 1. Energy Losses During Switching-Off Transition
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© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.1 • 4/3/09
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