Fairchild SPT5240 User Manual

www.fairchildsemi.com

SPT5240

10-bit, 400 MWPS Current Output
Digital-to-Analog Converter

Features

• 400 MWPS update rate

• Complementary current outputs

• +3.3 V power supply

• Low power dissipation:
149mW (typ) @ƒ

• Excellent AC performance:
SFDR = 58dBc for ƒ

• Internal reference

= 400MHz and 12mA output

CLK

= 400MHz and ƒ

CLK

Applications

• Battery-operated devices

• Portable RF devices

• Set top boxes

• Video displays

• Broadband RF

• High-speed test equipment

Functional Block Diagram

= 1.27 MHz

OUT

PWD

Description

The SPT5240 is a 10-bit digital-to-analog converter that
performs at an update rate of 400M words per second. The
architecture achieves excellent high-frequency performance
with very low power dissipation. This makes it ideal for all
types of battery-operated equipment requiring high-speed
digital-to-analog conversion.

The SPT5240 operates over an extended industrial
temperature range from -40°C to +85°C and is available in a
32-lead LQFP package.

DV

DD

AV

DD

I

SET

D0 – D9

CLK

10 Bits

Reference

Circuit

10-bit

Current Output

DAC

DGND AGND

IO

IO

P

N

REV. 1 June 2003

(

DATA SHEET SPT5240

Electrical Specifications

T

= 25°C, AV

A

I

= 20mA, R

OUT

Parameter Conditions Test Level Min Typ Max Units

DC Performance

Resolution 10 Bits

Differential Linearity Error (DLE) DC at IO

Integral Linearity Error (ILE) DC at IO

Offset Error DC at both outputs I -.005 +.005 %FS

Full Scale Error DC at both outputs I -15 +15 %FS

Gain Error DC at both outputs I -15 +15 %FS

Maximum Full Scale Output Current V 30 mA

Output Compliance Voltage V 1.5 V

Output Impedance Full-scale output V 250 k

Gain Error Tempco V ±300 ppm

AC Performance

Maximum Clock Rate IV 400

Glitch Energy Major code transition V 7 pV-s

Settling Time (t

Output Rise Time V 1.3 ns

Output Fall Time V 1.5 ns

Output Delay Time (t

Spurious Free Dynamic Range (SFDR)

Total Harmonic Distortion (THD) V -55 dBc

Digital and Clock Data Input

V

Minimum V 2 V

IH

V

Maximum V 1 V

IL

Logic “1” Current I -10 +10 µ A

Logic “0” Current I -10 +10 µ A

Input Setup Time (t

Input Hold Time (t

Clock Feedthrough V -29 dBFS

= 3.3V, DV

DD

= 50 Ω ; unless otherwise noted)

L

) See Figure 1, major code trans. V 7.5 ns

settling

D

= 3.3V,

DD

ƒ

= 1.27MHz,

OUT

ƒ

= 400MHz, Clock Duty Cycle = 50%,

CLK

N

N

I-1 2LSB

I-4±1.34 4 LSB

) See Figure 1 V 1.8 ns

V58dBc

) See Figure 1 V 1 ns

S

) See Figure 1 V 1 ns

H

Ω

FS/°C

MHz

TEST LEVEL CODES

All electrical characteristics are subject to the following conditions:

All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing
actually performed during production and Quality Assurance inspection.

LEVEL TEST PROCEDURE

I 100% production tested at the specified temperature.

IV Parameter is guaranteed by design or characterization data.

V Parameter is a typical value for information purposes only.

2

REV. 1 June 2003

(

SPT5240 DATA SHEET

Electrical Specifications

T

= 25°C, AV

A

I

= 20mA, R

OUT

= 3.3V, DV

DD

= 50 Ω ; unless otherwise noted)

L

= 3.3V,

DD

(Continued)

ƒ

= 1.27MHz,

OUT

ƒ

= 400MHz, Clock Duty Cycle = 50%,

CLK

Parameter Conditions Test Level Min Typ Max Units

Power Supply Requirements

Supply Voltage AV

DD

= DV

DD

IV 3.0 +3.3 3.6 V

Supply Current Sleep Mode

AV

DD

DV

DD

Power Dissipation 20mA I

25MHz Clock V 9.5 mA

25MHz Clock V 200

IV 170 195 215 mW

V 149 mW

12mA I

OUT

OUT

µ A

TEST LEVEL CODES

All electrical characteristics are subject to the following conditions:

All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing
actually performed during production and Quality Assurance inspection.

LEVEL TEST PROCEDURE

I 100% production tested at the specified temperature.

IV Parameter is guaranteed by design or characterization data.

V Parameter is a typical value for information purposes only.

REV. 1 June 2003

3