Fairchild RMBA19500A service manual

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RMBA19500A

PCS1900 2 Watt GaAs MMIC Power Amplifier

RMBA19500A

May 2004

General Description

The RMBA19500A is a highly linear Power Amplifier. The
two stage circuit uses our pHEMT process. It has been

Features

•2 Watt linear output power at 36 dBc ACPR1 for CDMA
operation

designed for use as a driver stage for PCS1900 base
stations, or as the output stage for Micro- and Pico-Cell
base stations. The amplifier has been optimized for high
linearity requirements for PCS operation.

• OIP3 ≥ 43 dBm at 27 and 30 dBm output

• Small Signal Gain of > 30 dB

• Small outline SMD package

Absolute Ratings

Symbol Parameter Ratings Units

Vd Drain Supply Voltage

1

+10 V

Vg Gate Supply Voltage (max absolute) -5 V

P

IN

T

C

T

STG

Electrical Characteristics

RF Input Power (from 50 Ω source) +5 dBm

Operating Case Temperature Range -30 to +85 °C

Storage Temperature Range -40 to +100 °C

2

Parameter Min Typ Max Units

Frequency Range 1930 1990 MHz

Gain (Small Signal) Over 1930–1990 MHz 30 dB

Gain Variation
Over Frequency Range
Over Temperature Range

±1.0
±1.5

dB
dB

Noise Figure 6 dB

P1dB Output 30 dBm

Output Power @ CDMA

3

33 dBm

PAE @ 33 dBm Pout 24 %

4

OIP3

43 45 dBm

Drain Voltage (Vdd) 7.0 V

Gate Voltage (VG1, 2 and VG3)

Quiescent currents (Idq1, 2 and Idq3)

Thermal Resistance (Channel to Case) R

Notes:

1. Only under quienscent conditions—no RF applied.

2. V

= 7.0V, T

DD

3. 9 Channel Forward Link QPSK Source; 1.23 Mbps modulation rate. CDMA ACPR1 is measured using the ratio of the average power within the 1.23 MHz channel
at band center to the average power within a 30 KHz bandwidth at an 885 KHz offset. Minimum CDMA output power is met with ACPR1 > 36 dBc.

4. OIP3 specifications are achieved for power output levels of 27 and 30 dBm per tone with tone spacing of 1.25 MHz at band-center with adjusted supply and bias
conditions of Vdd = 6.5V and IdqTotal = 625mA (see Note 5).

5. VG1,2 and VG3 must be individually adjusted to achieve IDQ1,2 and IDQ3. A single VGG bias supply adjusted to achieve IDQTOTAL = 625mA can be used with
nearly equivalent performance. Values for IDQ1,2 and IDQ3 shown have been optimized for CDMA operation. IDQ1, 2 and IDQ3 (or IDQTOTAL) can be adjusted
to optimize the linearity of the amplifier for other modulation systems.

The device requires external input and output matching to 50 Ω as shown in Figure 3 and the Parts List.

= 25°C. Part mounted on evaluation board with input and output matching to 50 Ω .

C

5

-2 -0.25 V

5

JC

180, 445 mA

11 °C/W

©2004 Fairchild Semiconductor Corporation

RMBA19500A Rev. C

Application Information

CAUTION: THIS IS AN ESD SENSITIVE DEVICE

The following describes a procedure for evaluating the RMBA19500A, a monolithic high efficiency power amplifier, in a
surface mount package, designed for use as a driver stage for PCS1900 Base station or as the final output stage for Micro­and Pico-Cell base stations. Figure 1 shows the package outline and the pin designations. Figure 2 shows the functional
block diagram of the packaged product. The RMBA19500A requires external passive components for DC bias and RF input
and output matching circuits as shown in Figure 3 and the Parts List. A recommended schematic circuit is shown in Figure

3. The gate biases for the three stages of the amplifier may be set by simple resistive voltage dividers. Figure 4 shows a

typical layout of an evaluation board, corresponding to the schematic circuits of Figure 3. The following designations should
be noted:

(1) Pin designations are as shown in Figure 2.

(2) Vg1, Vg2, and Vg3 are the Gate Voltages (negative) applied at the pins of the package.

(3) Vgg1, 2, and Vgg3 are the negative supply voltages at the evaluation board terminals (Vg1 and Vg2 are tied together).

(4) Vd1, Vd2, and Vd3 are the Drain Voltages (positive) applied at the pins of the package.

(5) Vdd is the positive supply voltage at the evaluation board terminal (Vd1, Vd2, and Vd3 are tied together).

Note: The base of the package must be soldered on to a heat sink for proper operation.

Top View

RMBA19500A

0.030

8

0.010

Dimensions in inches

0.200 SQ.

65

4

2

0.011

0.015

3

2

1

0.020

7

RMBA19500A

9

11 12

10

3

1

Plastic Lid

0.075 MAX

0.230

0.246

0.282

Side Section

Bottom View

6

45

12 11 10

Pin Description

1 RF Out & Vd3
2 RF Out & Vd3
3 RF Out & Vd3
4 VD1
5 GND
6 VG1
7 RF In
8 GND
9 VG2
10 VD2
11 GND
12 VG3
13 GND

7

8

9

0.041

Figure 1. Package Outline and Pin Designations

©2004 Fairchild Semiconductor Corporation RMBA19500A Rev. C

RMBA19500A

RFIN

J1

L4

5.6nH

P1
VG1, VG2

P3
GND

RF IN

Pin #7

C1
10pF

R2
1kΩ

C6

0.1µF

MMIC CHIP

R1
20Ω

R7
1KΩ

Vd1

Pin #4

Vg1

Pin #6

Vd2

Pin #

Vg 2

Pin # 9

10

GND

Pin #5, 8, 11, 13

Vg 3

Pin #

12

Figure 2. Functional Block Diagram

R4
30Ω

L1

C5
1500pF

R9
300Ω

5.6nH

R3
910Ω

R6

1.1KΩ

R5
20Ω

C4
1500pF

Fairchild

RMBA19500A

L2

5.6nH

R8
390Ω

RF OUT & Vd3
Pin #1, 2, 3

C3
1500pF

L3
10nH

C8

4.7µF

C7

0.1µF

C9

2.2pF

C14

4.7µF

C15

4.7µF

C2

10.0pF

C10

2.2pF

C11

4.7µF

P2

VGG3

RFOUT

J2

P4
VD1, 2, 3

Figure 3. Schematic of Application Circuit Showing External Components

©2004 Fairchild Semiconductor Corporation RMBA19500A Rev. C