Fairchild RFD14N05L, RFD14N05LSM, RFP14N05L service manual

RFD14N05L, RFD14N05LSM, RFP14N05L

Data Sheet November 2004

14A, 50V, 0.100 Ohm, Logic Level,
N-Channel Power MOSFETs

These are N-channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. This performance is accomplished
through a special gate oxide design which provides full rated
conductance at gate bias in the 3V-5V range, thereby
facilitating true on-off power control directly from logic level
(5V) integrated circuits.

Formerly developmental type TA09870.

Ordering Information

PART NUMBER PACKAGE BRAND

RFD14N05L TO-251AA 14N05L
RFD14N05LSM TO-252AA 14N05L
RFP14N05L TO-220AB F14N05L

NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05LSM9A.

Features

• 14A, 50V

•r

• Temperature Compensating PSPICE

DS(ON)

= 0.100Ω

®

Model

• Can be Driven Directly from CMOS, NMOS, and
TTL Circuits

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

C Operating Temperature

•175

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

D

G

S

Packaging

DRAIN (FLANGE)

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

GATE

DRAIN (FLANGE)

GATE

SOURCE

JEDEC TO-220AB

SOURCE

DRAIN

GATE

DRAIN (FLANGE)

©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1

RFD14N05L, RFD14N05LSM, RFP14N05L

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFD14N05L, RFD14N05LSM,

RFP14N05L UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (R

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V

GS

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

DSS

DGR

GS

DM

AS

J, TSTG

D

D

Refer to Peak Current Curve

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specificat ion is not implied.

L

pkg

50 V
50 V

±10 V

14

Refer to UIS Curve

48

0.32

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

= 25oC to 150oC.

1. T

J

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

(OFF)
g(TOT)VGS

Gate Charge at 5V Q
Threshold Gate Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

R

DSSID

DSS

GSS

(ON)

r

f

g(5)

g(TH)

ISS
OSS
RSS

θJC

θJA

θJA

= 250µA, VGS = 0V, Figure 13 50 - - V

= VDS, ID = 250µA, Figure12 1 - 2 V

VDS = 40V, VGS = 0V - - 1 µA

= 40V, VGS = 0V, TC = 150oC--50µA

V

DS

VGS = ±10V - - ±100 nA

= 14A, VGS = 5V, Figures 9, 11 - - 0.100 Ω

VDD = 25V, ID = 7A,
R

= 3.57Ω, VGS = 5V,

L

R

= 0.6Ω

GS

--60ns

-13 - ns

-24 - ns

-42 - ns

-16 - ns

- - 100 ns

= 0V to 10V VDD = 40V, ID = 14A,

R

= 2.86Ω

VGS = 0V to 5V - - 25 nC
VGS = 0V to 1V - - 1.5 nC

L

Figures 20, 21

VDS = 25V, VGS = 0V, f = 1MHz
Figure 14

- - 40 nC

- 670 - pF

- 185 - pF

-50 - pF

- - 3.125oC/W
TO-251 and TO-252 - - 100
TO-220 - - 80

o
o

C/W
C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V
Diode Reverse Recovery Time t

NOTES:

2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%.

3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).

©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1

ISD = 14A - - 1.5 V

SD

ISD = 14A, dISD/dt = 100A/µs - - 125 ns

rr

5

5

0

RFD14N05L, RFD14N05LSM, RFP14N05L

Typical Performance Curves Unless Otherwise Specified

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0

0

25 50 75 100

TC, CASE TEMPERA TURE (oC)

125

150

FIGURE 1. NORMALIZED POWER DISSIPA TION vs CASE

TEMPERATURE

2

1

0.5

0.2

0.1

0.1

, NORMALIZED

JC

θ

Z

THERMAL IMPEDANCE

0.01
10

0.05

0.02

0.01
SINGLE PULSE

-5

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

16

12

8

, DRAIN CURRENT (A)

4

D

I

17

0

25 50 75 100

TC, CASE TEMPERATURE (oC)

125

150

17

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

TEMPERATURE

P

DM

t

1

t

2

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-2

10

-1

10

1/t2

x R

JC

θ

0

10

+ T

JC

C

θ

1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

100

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE

1

LIMITED BY r

0.5
1

TJ = MAX. RATED

DS(ON)

10

VDS, DRAIN TO SOURCE VOLTAGE (V)

TC = 25oC

100µs

1ms

10ms
100ms

DC

10

200

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

100

, PEAK CURRENT CAPABILITY (A)

DM

I

TC = 25oC

10

-5

10

FOR TEMPERAT URES
ABOVE 25
CURRENT AS FOLLOWS:

VGS = 5V
VGS = 10V

-4

10

-3

10

t, PULSE WIDTH (s)

-2

10

I = I

o

C DERATE PEAK

175 - T

25

150

-1

10

C

0

10

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

©2004 Fairchild Semiconductor Corporation RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1

1