Fairchild RFD14N05, RFD14N05SM service manual

RFD14N05, RFD14N05SM

Data Sheet

14A, 50V, 0.100 Ohm, N-Channel Power MOSFETs

These are N-channel power MOSFETs manufactured using the MegaFET process. This proces s, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits.

Formerly developmental type TA09770.

Ordering Information

PART NUMBER PACKAGE BRAND

RFD14N05 TO-251AA F14N05 RFD14N05SM TO-252AA F14N05

NOTE: When ordering, use the ent ire part number . Add t he suffix 9A t o obtain the TO -252AA variant in t he tape and reel , i.e., RF D14N05SM9A.

February 2004

Features

• 14A, 50V

•r

• Temperature Compensating PSPICE

DS(ON)

= 0.100Ω

®

Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

o

•175

C Operating Temperature

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”

Symbol

D

G

Packaging

DRAIN (FLANGE)

S

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

GATE

SOURCE

DRAIN (FLANGE)

RFD14N05, RFD14N05SM

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

RFD14N05, RFD14N05SM UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (R

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

GS

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

DSS

DGR

GS

DM

AS

J, TSTG

D

Refer to Peak Current Curve

D

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

50 V 50 V

±20 V

14

Refer to UIS Curve

48

0.32 -55 to 175

300 260

A

W

W/oC

o

C

o

C

o

C

NOTE:

= 25oC to 150oC.

1. T

J

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV Gate Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I Drain to Source On Resistance (Note 2) r

DS(ON)ID

Turn-On Time t Turn-On Delay Time t

d(ON)

Rise Time t Turn-Off Delay Time t

d(OFF)

Fall Time t Turn-Off Time t Total Gate Charge Q

g(TOT)VGS

Gate Charge at 5V Q Threshold Gate Charge Q

Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Thermal Resistance Junction to Case R Thermal Resistance Junction to Ambient R

DSSID

DSS

GSS

ON

r

f

OFF

g(10)VGS

g(TH)VGS

ISS

OSS

RSS

θJC θJA

= 250µA, VGS = 0V (Figure 9) 50 - - V

= VDS, ID = 250µA2-4V VDS = Rated BV V

= 0.8 x Rated BV

DS

, VGS = 0V - - 25 µA

DSS

, VGS = 0V, TC = 150oC - - 250 µA

DSS

VGS = ±20V - - ±100 nA

= 14A, VGS = 10V, (Figure 11) - - 0.100 Ω

VDD = 25V, ID ≈ 14A, VGS = 10V,

= 25Ω, RL = 1.7Ω

R

GS

(Figure 13)

- - 60 ns

-14- ns

-26- ns

-45- ns

-17- ns

- - 100 ns

= 0V to 20V VDD = 40V, ID = 14A,

R

= 2.86Ω

= 0V to 10V - - 25 nC

= 0V to 2V - - 1.5 nC

L

= 0.4mA

I

g(REF)

(Figure 13)

VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)

- - 40 nC

- 570 - pF

- 185 - pF

-50- pF

- - 3.125oC/W

- - 100

o

C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V Diode Reverse Recovery Time t

NOTES:

2. Pulse Te st: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%.

3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5).

ISD = 14A - - 1.5 V

SD

ISD = 14A, dISD/dt = 100A/µs - - 125 ns

rr

RFD14N05, RFD14N05SM

Typical Performance Curves Unless Otherwise Specified

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

25 50 75 100

TC, CASE TEMPERATURE (oC)

125

150

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE

1

0.5

0.2

0.1

THERMAL IMPEDANCE

0.1

0.05

0.02

0.01

NORMALIZED

Z

JC,

θ

SINGLE PULSE

0.01

-5

10

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

16

12

8

, DRAIN CURRENT (A)

4

D

I

1750

0

25 50 75 100

TC, CASE TEMPERATURE (oC)

125

150

175

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

t

1

t

2

NOTES: DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-2

10

-1

10

1/t2

x R

JA

θ

0

10

+ T

JA

A

θ

1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

, DRAIN CURRENT (A) I

100

D

10

OPERATION IN THIS AREA MAY BE LIMITED BY r

1

DS(ON)

10

VDS, DRAIN TO SOURCE VOLTAGE (V)

TJ = MAX RATED SINGLE PULSE

= 25oC

T

C

100µs

1ms

10ms

DC

100ms

100

TRANSCONDUCTANCE

, PEAK CURRENT CAPABILITY (A)

MAY LIMIT CURRENT IN THIS REGION

DM

I

10

-5

10

VGS = 20V

VGS = 10V

-4

10

FOR TEMPERATURES ABOVE 25 CURRENT AS FOLLOWS:

-3

10

t, PULSE WIDTH (s)

-2

10

o

C DERATE PEAK

175 T



II

---------------------

=



25

150



-1

10

–

C

0

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

1

RFD14N05, RFD14N05SM

Typical Performance Curves Unless Otherwise Specified (Continued)

50

STARTING TJ = 25oC

10

STAR TING TJ = 150oC

If R = 0

, AVALANCHE CURRENT (A)

tAV = (L)(IAS)/(1.3*RATED BV

AS

I

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

1

0.01

0.1 1 10

tAV, TIME IN AVALANCHE (ms)

DSS

- VDD)

DSS-VDD

) +1]

NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

35

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

30

25

20

15

= 15V

V

DD

-55oC

-25oC

175

o

C

35

= 20V

V

GS

30

25

20

15

10

, DRAIN CURRENT (A)

D

I

5

0

2

VDS, DRAIN TO SOURCE VOLTAGE (V)

V

= 10V

GS

VGS = 8V

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

468

FIGURE 7. SATURATION CHARACTERISTICS

2.0 ID = 250µA

1.5

1.0

= 25oC

T

C

VGS = 7V

= 6V

V

GS

VGS = 5V

= 4.5V

V

GS

10

, DRAIN TO SOURCE CURRENT (A)

5

DS(ON)

I

0

0468102

VGS, GATE TO SOURCE VOLTAGE (V)

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 T

, JUNCTION TEMPERATURE (oC)

J

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

2.0 VGS = VDS, ID = 250µA

1.5

1.0

, NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

GS(TH)

V

0

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

200

2.5

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

= 10V, ID = 14A

V

GS

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

200

FIGURE 10. NORMALIZED GATE THRESHOLD V OLTA GE vs

JUNCTION TEMPERATURE

FIGURE 11. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

RFD14N05, RFD14N05SM

Typical Performance Curves Unless Otherwise Specified (Continued)

700

C

600

500

400

300

200

C, CAPACITANCE (pF)

100

0

0 5 10 15 20 25

ISS

C

OSS

C

RSS

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

VGS = 0V, f = 1MHz

= CGS + C

C C C

ISS RSS OSS

= C ≈ CDS + C

GD

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

Test Circuits and Waveforms

V

DS

L

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

AS

R

G

DUT

+

-

60

V

DD

= BV

DSS

VDD = BV

DSS

45

30

0.75 BV

DSS

0.50 BV

DSS

0.25 BV

15

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

I

GREF()

--------------------- -

20

I

GACT()

RL = 3.57Ω I

= 0.4mA

G(REF)

V

= 10V

GS

t, TIME (µs)

DSS

I

GREF()

--------------------- -

80

I

GACT()

10

7.5

5.0

2.5

0

, GATE TO SOURCE VOLTAGE (V)

GS

V

NOTE: Refer to Fairchild Application Notes AN7254 and AN7260,

FIGURE 13. NORMALIZED SWITCHING WA VEFORMS FOR

CONSTANT CURRENT GATE DRIVE

BV

DSS

t

P

I

AS

V

DD

V

DS

V

DD

0V

P

I

AS

0.01Ω

0

t

AV

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

10%

d(ON)

90%

50%

t

10%

r

PULSE WIDTH

V

DS

V

DS

R

DUT

L

+

V

DD

-

0

V

GS

0

V

GS

R

GS

V

GS

t

d(OFF)

90%

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

t

OFF

50%

t

f

90%

10%

RFD14N05, RFD14N05SM

Test Circuits and Waveforms (Continued)

V

DS

R

L

V

GS

DUT

I

G(REF)

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS

+

V

-

DD

V

DD

V

0

I

G(REF)

0

GS

V

= 2V

GS

Q

g(TH)

Q

g(10)

Q

g(TOT)

V

DS

V

= 20V

GS

VGS = 10V

PSPICE Electrical Model

.SUBCKT RFD14N05 2 1 3 ; rev 9/12/94

CA 12 8 8.84e-10 CB 15 14 9.34e-10 CIN 6 8 5.2e-10

DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 62.87 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1

IT 8 17 1

LDRAIN 2 5 1e-9 LGATE 1 9 4.34e-9 LSOURCE 3 7 3.79e-9

MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01

RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 2.2e-3 RGATE 9 20 5.64 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 42.3e-3 RVTO 18 19 RVTOMOD 1

GATE

1

LGATE

RFD14N05, RFD14N05SM

DPLCAP

RSCL2

-

6 8

+

RIN

6 8

-

VTO

+

6

CIN

15

14 13

S2BS1B

13

CB

+

-

RGATE

EVTO

+

209

S1A S2A

12

CA

10

ESG

-

18

8

13

8

EGS EDS

5

LDRAIN

RSCL1

51

+

5

51

50 RDRAIN

16

21

MOS1

14 5 8

ESCL

8

DBREAK

11

EBREAK

MOS2

RSOURCE

17 18

+

17 18

-

RBREAK

7

IT

DBODY

LSOURCE

RVTO

19

VBAT

+

DRAIN 2

3

SOURCE

S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1 VTO 21 6 0.82

ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/50,6))}

.MODEL DBDMOD D (IS = 1.5e-13 RS = 10.9e-3 TRS1 = 2.3e-3 TRS2 = -1.75e-5 CJO = 6.84e-10 TT = 4.2e-8) .MODEL DBKMOD D (RS = 4.15e-1 TRS1 = 3.73e-3 TRS2 = -3.21e-5) .MODEL DPLCAPMOD D (CJO = 26.2e-11 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 3.91 KP = 12.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.73e-4 TC2 = 2.12e-6) .MODEL RDSMOD RES (TC1 = 5.0e-3 TC2 = 2.53e-5) .MODEL RSCLMOD RES (TC1 = 2.05e-3 TC2 = 1.35e-5) .MODEL RVTOMOD RES (TC1 = -4.44e-3 TC2 = -6.45e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.29 VOFF= -3.29) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.29 VOFF= -5.29) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.25 VOFF= 2.75) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.75 VOFF= -2.25)

.ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub -circuit for the Po wer MOSFET Featuri ng Global Temperature Options; written by William J. Hepp and C. Frank Wheatley.

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ ActiveArray™ Bottomless™ CoolFET™ CROSSVOL T™ DOME™ EcoSPARK™ E2CMOS EnSigna

TM

FACT™

FACT Quiet Series™



FAST FASTr™

FPS™

FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ I2C™ ImpliedDisconnect™

Across the board. Around the world.™ The Power Franchise™ Programmable Active Droop™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE T O ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY , FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT

CONVEY ANY LICENSE UNDER ITS PA TENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

ISOPLANAR™

LittleFET™

MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC OPTOPLANAR™ P ACMAN™



POP™

Power247™

PowerSaver™ PowerTrench



QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ SILENT SWITCHER SMART ST ART™ SPM™



Stealth™ SuperFET™

SuperSOT™-3

SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic



TINYOPTO™ TruTranslation™ UHC™



UltraFET



VCX™

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORA TION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

PRODUCT STA TUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Formative or In Design

First Production

Full Production

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or

effectiveness.

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. I8

Fairchild RFD14N05, RFD14N05SM service manual

Specifications and Main Features

Frequently Asked Questions

User Manual

RFD14N05, RFD14N05SM

Features

Packaging

JEDEC TO-251AA JEDEC TO-252AA

RFD14N05, RFD14N05SM

Refer to Peak Current Curve

Refer to UIS Curve

0.32

-55 to 175

W/oC

VGS = ±20V - - ±100 nA

= 14A, VGS = 10V, (Figure 11) - - 0.100 Ω

Source to Drain Diode Specifications

RFD14N05, RFD14N05SM

RFD14N05, RFD14N05SM

RFD14N05, RFD14N05SM

RFD14N05, RFD14N05SM

RFD14N05, RFD14N05SM