Fairchild RC5050, RC5051 User Manual
www.fairchildsemi.com
Application Note 50
Implementing the RC5050 and RC5051 DC-DC
Converters on Pentium
®
Pro Motherboards
Introduction
This document describes how to implement a switching voltage regulator using an RC5050 or an RC5051 high speed
controller, a power inductor, a Schottky diode, appropriate
capacitors, and external power MOSFETs. This regulator
forms a step down DC-DC converter that can deliver up to
14.5A of continuous load current at voltages ranging from
1.3V to 3.5V. A specific application circuit, design considerations, component selection, PCB layout guidelines, and performance evaluations are covered in detail.
In the past 10 years, microprocessors have ev olved at such an
exponential rate that a modern chip can rival the computing
power of a mainframe computer. Such evolution has been
possible because of the increasing numbers of transistors that
processors integrate. Pentium CPUs, for example, integrate
well over 5 million transistors on a single piece of silicon.
To integrate so many transistors on a piece of silicon, their
physical geometry has been reduced to the sub-micron level.
As a result of each geometry reduction, the corresponding
operational voltage for each transistor has also been reduced.
The changing CPU voltage demands the design of a programmable power supply—a design that is not completely
re-engineered with every change in CPU voltage.
The voltage range of the CPU has shown a downw ards trend
for the past 5 years: from 3.3V for the Pentium, to 3.1V for
the Pentium Pro, and to 1.8V for future processors. With this
trend in mind, Raytheon Electronics has designed the
RC5050 and RC5051 controllers. These controllers integrate
the necessary programmability to address the changing
power supply requirements of lower voltage CPUs.
Previous generations of DC-DC converter controllers were
designed with fixed output voltages adjustable only with a
set of external resistors. In a high volume production environment (such as with personal computers), however, a CPU
voltage change requires a CPU board re-design to accommodate the new voltage requirement. The 5-bit DAC in the
RC5050 and the RC5051 reads the voltage ID code that is
programmed into modern processors and provides the appropriate CPU voltage. In this manner, the PC board does not
have to be re-designed each time the CPU voltage changes.
The CPU can thus automatically configure its own required
supply voltage.
Intel Pentium Pro Processor Power
Requirements
Refer to Intel’s AP-523 Application Note, Pentium® Pro
Processor Power Distribution Guidelines, November 1995
(order number 242764-001), as a basic reference. The specifications contained in this document have been modified
slightly from the original Intel document to include updated
specifications for more recent processors. Please contact
Intel Corporation for specific details.
Input V oltages
A v ailable inputs are +12V ±5% and +5V ±5%. Either one or
both of these inputs can be used by the DC-DC converter.
The input voltage requirements for Raytheon’s RC5050
and RC5051 DC-DC converters are listed in Table 1.
Table 1. Input Voltage Requirements
MOSFET
Part # Vcc for IC
RC5050
RC5051
+5V ±5% +5V ±5% 12V ±5% or
Drain
Pentium Pro DC Power Requirements
Refer to Table 2, Intel Pentium Pro and OverDrive® Processor Power Specifications. For a motherboard designs without
a standard VRM (Voltage Regulator Module) socket, the
on-board DC-DC converter must supply a minimum of
13.9A of current @2.5V and 12.4A of current @3.3V. For a
Flexible Motherboard design, the on-board DC-DC converter must supply 14.5A maximum ICCP.
DC V oltage Regulation
As indicated in Table 2, the voltage level supplied to the
CPU must be within ±5% of its nominal setting. Voltage regulation limits must include:
• Output load ranges specified in Table 2
• Output ripple/noise
• DC output initial voltage set point
• Temperature and w arm up drift (Ambient +10°C to +50°C
at full load with a maximum rate of change of 5°C per 10
minutes minimum but no more than 10°C per hour)
• Output load transient with:
Slew rate >30A/µs at converter pins
Range: 0.3A - ICCP Max (as defined in Table 2).
MOSFET
Gate Bias
+5V ±5%
Rev. 1.1.0
AN50 APPLICATION NOTE
Table 2. Intel Pentium Pro and OverDrive® Processor Power Specifications
Voltage
Specification,
CPU Model, Features
VCCP (VDC)
150MHz, 256K L2 Cache 3.1 ±5% 9.9 29.2
166MHz, 512K L2 Cache 3.3 ±5% 11.2 35.0
180MHz, 256K L2 Cache 3.3 ±5% 10.1 31.7
200MHz, 256K L2 Cache 3.3 ±5% 11.2 35.0
200MHz, 512K L2 Cache 3.3 ±5% 12.4 37.9
OverDrive Processors
150Mhz
2.5 ±5% 11.2
180Mhz
200Mhz
Flexible Motherboard
Notes:
1. Maximum power values are measured at typical V
2. Flexible motherboard specifications are recommendations only. Actual specifications are subject to change.
2
2.4-3.5 ±5% 14.5 45.0
P to take into account the thermal time constant of the CPU package.
CC
Maximum
Current,
ICCP (A)
12.5
13.9
Maximum Thermal
Design power
1
(W)
26.7
29.7
32.9
Output Ripple and Noise
Ripple and noise are defined as periodic or random signals
over the frequency band of 20Mhz at the output pins. Output
ripple and noise requirements of ±13mV must be met
throughout the full load range and under all specified input
voltage conditions.
Efficiency
The efficiency of the DC-DC converter must be greater than
80% at maximum output current and greater than 40% at low
current draw.
Processor Voltage Identification
There are four voltage identification Pins, VID3-VID0, on
the Pentium Pro processor package which can be used to
support automatic selection of the power supply voltage.
These pins are internally unconnected or are shorted to
ground (VSS). The logic status of the VID pins defines the
voltage required by the processor. In order to address future
low voltage microprocessors, the RC5050 and RC5051
include a VID4 input bit to extend the output voltage range
as low as 1.3V. The output voltage programming codes are
presented in Table 3. A “1” refers to an open pin and a ‘0’
refers to a short to ground.
Table 3. Output Voltage Programming
Codes
VID4 VID3 VID2 VID1 VID0 V
0 1 1 1 1 1.30V
0 1 1 1 0 1.35V
0 1 1 0 1 1.40V
0 1 1 0 0 1.45V
0 1 0 1 1 1.50V
0 1 0 1 0 1.55V
OUT
to CPU
Table 3. Output Voltage Programming
Codes
Note:
1. 0 = processor pin is tied to GND
(continued)
VID4 VID3 VID2 VID1 VID0 V
OUT
0 1 0 0 1 1.60V
0 1 0 0 0 1.65V
0 0 1 1 1 1.70V
0 0 1 1 0 1.75V
0 0 1 0 1 1.80V
0 0 1 0 0 1.85V
0 0 0 1 1 1.90V
0 0 0 1 0 1.95V
0 0 0 0 1 2.00V
0 0 0 0 0 2.05V
1 1 1 1 1 No CPU
1 1 1 1 0 2.1V
1 1 1 0 1 2.2V
1 1 1 0 0 2.3V
1 1 0 1 1 2.4V
1 1 0 1 0 2.5V
1 1 0 0 1 2.6V
1 1 0 0 0 2.7V
1 0 1 1 1 2.8V
1 0 1 1 0 2.9V
1 0 1 0 1 3.0V
1 0 1 0 0 3.1V
1 0 0 1 1 3.2V
1 0 0 1 0 3.3V
1 0 0 0 1 3.4V
1 0 0 0 0 3.5V
1 = processor pin is open.
to CPU
2
APPLICATION NOTE AN50
I
L
VINV
OUT
–( )T
ON
L1
-----------------------------------------------=
V
OUT
V
IN
T
ON
T
S
-----------
=
I/O Controls
In addition to the Voltage Identification, there are several signals that control the DC-DC converter or provide feedback
from the DC-DC converter to the CPU. They are PowerGood (PWRGD), Output Enable (OUTEN), and Upgrade
Present (UP#). These signals will be discussed later.
RC5050 and RC5051 Description
Simple Step-Down Converter
S1
V
IN
Figure 1. Simple Buck DC-DC Converter
Figure 1 illustrates a step-down DC-DC converter with no
feedback control. The derivation of the basic step-down converter is the basis for the design equations for the RC5050
and RC5051. Referring to Figure 1, the basic operation
begins by closing the switch S1. When S1 is closed, the input
voltage V
is impressed across inductor L1. The current
IN
flowing in this inductor is given by the following equation:
where T
is the duty cycle (the time when S1 is closed).
ON
When S1 opens, the diode D1 conducts the inductor
current and the output current is delivered to the load according to the following equation:
V
-------------------------------------------=
I
L
–( )
OUTTSTON
L1
whereTS is the overall switching period and (TS - TON) is the
time during which S1 is open.
D1
L1
C1 RL Vout
65-5050-06
+
–
The RC5050 and RC5051 Controllers
The RC5050 is a programmable non-synchronous DC-DC
controller IC. The RC5051 is a synchronous version of the
RC5050. When designed around the appropriate external
components, either of these devices can be configured to
deliver more than 14.5A of output current. The RC5050 and
RC5051 utilize both current-mode and voltage-mode PWM
control to create an integrated step-down voltage regulator.
The key differences between the RC5050 and RC5051 are
listed in Table 4.
Table 4. RC5050 and RC5051 Differences
RC5051 RC5050
Operation Synchronous Non-Synchronous
Package 20-SOIC 20-SOIC
Output Enable/
Yes Yes
Disable
Main Control Loop
Refer to the RC5051 Block Diagram illustrated in Figure 2.
The control loop of the regulator contains two main sections;
the analog control block and the digital control block. The
analog section consists of signal conditioning amplifiers
feeding into a set of comparators which provide the inputs to
the digital control block. The signal conditioning section
accepts inputs from the IFB (current feedback) and VFB
(voltage feedback) pins and sets up two controlling signal
paths. The voltage control path amplifies the VFB signal and
presents the output to one of the summing amplifier inputs.
The current control path takes the difference between the
IFB and VFB pins and presents the resulting signal to
another input of the summing amplifier. These two signals
are then summed together with the slope compensation input
from the oscillator. This output is then presented to a
comparator, which provides the main PWM control signal to
the digital control block.
The additional comparators in the analog control section set
the point at which the current limit comparator disables the
output drive signals to the external power MOSFETs.
By solving these two equations, we can arrive at the basic
relationship for the output voltage of a step-down con v erter:
In order to obtain a more accurate approximation for V
we must also include the forward voltage VD across diode
D1 and the switching loss, VSW. After taking into account
these factors, the new relationship becomes:
T
ON
-----------
V
OUT
VINVDVSW–+( )
V
–=
D
T
S
where VSW= MOSFET switching loss
= IL • R
DS,ON
OUT
The digital control block takes the comparator inputs and the
main clock signal from the oscillator to provide the appropriate pulses to the HIDRV and LODRV output pins. These
pins control the external power MOSFETs. The digital section utilizes high speed Schottky transistor logic, allowing
the RC5050 and the RC5051 to operate at clock speeds as
,
high as 1MHz.
High Current Output Drivers
The RC5051 contains two identical high current output
drivers that utilize high speed bipolar transistors in a
push-pull configuration. Each driver is capable of
delivering 1A of current in less than 100ns. Each driver’s
power and ground are separated from the chip’s power and
ground for additional switching noise immunity.
3
AN50 APPLICATION NOTE
+12V
RC5051
OSC
–
+
–
+
+5V
–
+
VREF
VID0
5-BIT
DAC
VID2 RSEL
VID1
VID3
1.24v
REFERENCE
Figure 2. RC5051 Block Diagram
The HIDRV driver has a power supply, VCCQP, supplied
from a 12V source as illustrated in Figure 2. The resulting
voltage is sufficient to provide the gate to source voltage to
the external MOSFET that is required to achieve a low
R
. Since the low side synchronous FET is referenced
DS,ON
to ground, there is no need to boost the gate drive voltage,
and its VCCP power pin can be tied to VCC.
Internal Voltage Reference
The reference included in the RC5050 and RC5051 is a precision band-gap voltage reference. The internal resistors are
precisely trimmed to provide a near zero temperature coefficient (TC). Added to the reference input is the resulting output from an integrated 5-bit DAC—provided in accordance
to the Pentium Pro specification guidelines. These guidelines
require the DC-DC converter output to be directly programmable via a 4-bit voltage identification (VID) code. This
code scales the reference voltage from 2.0V (no CPU) to
3.5V in 100mV increments. To target future generations of
low-voltage processors, the RC5050 and RC5051 incorporate a VID4 pin to allo w additional programmability between
1.3V and 2.05V. For guaranteed stable operation under all
operating conditions, a 0.1µF of decoupling capacitance
should be connected to the VREF pin. No load should be
imposed on this pin.
Power Good (PWRGD)
The RC5050 and RC5051 Power Good function is designed
in accordance with the Pentium Pro DC-DC converter specification to provide a constant voltage monitor on the VFB
pin. The circuit compares the VFB signal to the VREF volt-
–
+
DIGITAL
CONTROL
POWER
GOOD
PWRGD
VO
65-5051-01
age and outputs an active-low interrupt signal to the CPU
when the power supply voltage exceeds ±12% of nominal.
The Power Good flag provides no other control function to
the RC5050 or the RC5051.
Output Enable (OUTEN)
The DC-DC converter accepts an open collector signal for
controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the lo w
state.
Upgrade Present (UP#)
Intel specifications state that the DC-DC converter should
accept an open collector signal, used to indicate the presence
of an upgrade processor. The typical state is high (that is, a
standard processor is in the system). When in the low or
ground state (an OverDrive processor is present), the output
voltage must be disabled unless the conv erter can supply the
requirements of the OverDrive processor . When disabled, the
PWRGD output must be in the low state. Because the
RC5050 and RC5051 can supply the requirements of the
OverDrive processor, the #UP signal is not required.
Over-Voltage Protection
The RC5050 and RC5051 constantly monitor the output
voltage for protection against over voltage conditions. If the
voltage at the VFB pin e xceeds 20% of the selected program
voltage, an over-voltage condition is assumed and the chip
disables the output drive signal to the external MOSFET(s).
4
APPLICATION NOTE AN50
Short Circuit Protection
A current sense methodology is implemented to disable the
output drive signal to the MOSFET(s) when an over-current
condition is detected. The voltage drop created by the output
current flowing across a sense resistor is presented to an
internal comparator. When the voltage developed across the
sense resistor exceeds the comparator threshold voltage, the
chip reduces the output drive signal to the MOSFET(s).
The DC-DC converter returns to normal operation after the
fault has been removed, for either an over-voltage or a short
circuit condition.
Oscillator
The RC5050 and RC5051 oscillator section uses a fixed current capacitor charging configuration. An external capacitor
(C
) is used to preset the oscillator frequency between
EXT
200KHz and 1MHz. This scheme allows maximum flexibility in setting the switching frequency and in choosing external components.
In general, a lower operating frequency decreases the peak
ripple current flowing in the output inductor, thus allowing
the use of a smaller inductor value. Unfortunately, operation
at lower frequencies increases the amount of energy storage
that must be provided by the bulk output capacitors during
load transients due to slower loop response of the controller.
In addition, the efficiency losses due to switching of the
MOSFETs increase as the operating frequency is increased.
Thus, efficiency is optimized at lower operating frequencies.
An operating frequency of 300 kHz was chosen to optimize
efficiency while maintaining excellent regulation and transient performance under all operating conditions.
Design Considerations and
Component Selection
Figure 3 shows a typical non-synchronous application using
the RC5050. Figure 4 illustrates the synchronous application using the RC5051.
VREF
GND
+12V
+5V
C4
0.1µF
C7
0.1µF
L2
2.5µH
VID4
VID3
VID2
VID1
VID0
C1
1000 µF
C2
1000 µF
12
13
14
15
16
17
18
19
20
C3
1000µF
RC5050
C
EXT
100pF
C5
0.1µ F
1011
9
8
7
6
5
4
3
2
1
C10
0.1µ F
R5
47
C6
4.7µF
ENABLE
C12
1µF
D1
1N4691
IRF7413
R6
10K
M1
C11
0.1µ F
C8
0.1µ F
DS1
MBR2015CTL
VCC
PWRGD
M2
IRF7413
C9
0.1µF
L1
1.3µ H
R
6mΩ
SENSE
F
µ
1500
C13
1500 µF
C14
C15
VO
1500µF
1500µF
C16
Figure 3. Non-Synchronous DC-DC Converter Application Schematic Using the RC5050
5
AN50 APPLICATION NOTE
+12V
+5V
C4
0.1µF
VREF
GND
C7
0.1µF
L2
2.5µH
VID4
VID3
VID2
VID1
VID0
C1
1000 µF
C2
1000 µF
12
13
14
15
16
17
18
19
20
C3
1000µF
RC5051
C
100pF
C5
R5
0.1µ F
47
1011
9
8
7
6
5
4
3
2
1
EXT
C10
0.1µ F
C6
4.7µF
ENABLE
C12
1µF
D1
1N4691
IRF7413
10K
IRF7413
M3
R6
M1
C11
0.1µ F
C8
0.1µ F
VCC
PWRGD
M2
M4
IRF7413
0.1µF
IRF7413
1.3µ H
DS1
1N5817
C9
R
L1
6mΩ
SENSE
F
µ
1500
C13
1500 µF
C14
C15
VO
1500 µF
1500µF
C16
Figure 4. Synchronous DC-DC Converter Application Schematic Using the RC5051
6
APPLICATION NOTE AN50
MOSFET Selection Cosiderations
• Power package with low Thermal Resistance
• Drain current rating of 20A minimum
MOSFET Selection
• Drain-Source voltage > 15V.
This application requires N-channel Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics
are as follows:
The on-resistance (R
) is the primary parameter for
DS,ON
MOSFET selection. It determines the power dissipation
within the MOSFET and, therefore, significantly affects the
• Low Static Drain-Source On-Resistance,
R
< 37 mΩ (lower is better)
DS,ON
efficiency of the DC-DC converter. Table 5 is a selection
table for MOSFETs.
• Low gate drive voltage, VGS ≤ 4.5V
Table 3. MOSFET Selection Table
R
Manufacturer & Model # Conditions
Fuji
V
= 4V, ID = 17.5A TJ = 25°C 25 37 TO-220 Φ
GS
2SK1388
Siliconix
V
= 4.5V, ID = 5A TJ = 25°C 16.5 20 SO-8
GS
SI4410DY
National Semiconductor
V
= 5V, ID = 40A TJ = 25°C 13 15 TO-220 Φ
GS
1
TJ = 125°C 37 —
TJ = 125°C 28 34
NDP706AL
NDP706AEL TJ = 125°C 20 24
National Semiconductor V
NDP603AL T
National Semiconductor V
= 4.5V, ID = 10A TJ = 25°C 31 40 TO-220 Φ
GS
= 125°C 42 54 ΦJC= 2.5
J
= 5V, ID = 24A TJ = 25°C 22 25 TO-220 ΦJA= 62.5
GS
NDP606AL TJ = 125°C 33 40 Φ
Motorola V
= 5V, ID = 37.5A TJ = 25°C 6 9 TO-263 Φ
GS
MTB75N03HDL TJ = 125°C 9.3 14 (D2 PAK) Φ
Int. Rectifier V
= 5V, ID = 31A TJ = 25°C — 28 TO-220 Φ
GS
IRLZ44 TJ = 125°C — 46 Φ
Int. Rectifier V
= 4.5V, ID = 28A TJ = 25°C — 19 TO-220 Φ
GS
IRL3103S TJ = 125°C — 31 Φ
Intl Rectifier V
IRF7413 SMD
= 4.5V,
GS
ID = 3.7A
TA = 25°C 18 SO-8 Φ
DS, ON
(mΩ)
Package
(SMD)
Thermal
ResistanceTyp. Max.
= 75
JA
Φ
= 50
JA
= 62.5
JA
Φ
= 1.5
JC
= 62.5
JA
= 1.5
JC
= 62.5
JA
= 1.0
JC
= 62.5
JA
= 1.0
JC
= 62.5
JA
= 1.0
JC
= 50
JA
Note:
1. R
values at Tj = 125°C for most devices were extrapolated from the typical operating curves supplied by the
DS,ON
manufacturers and are approximations only.
7
AN50 APPLICATION NOTE
Two MOSFETs in parallel.
We recommend two MOSFETs used in parallel instead of
one single MOSFET. The following significant advantages
are realized using two MOSFETs in parallel:
• Significant reduction of Power dissipation.
Maximum current of 14A with one MOSFET:
P
MOSFET
= (I2 R
)(Duty Cycle) =
DS,ON
(14)2(0.050*)(3.3+0.4)/(5+0.4-0.35) = 7.2 W
With two MOSFETs in parallel:
P
MOSFET
= (I2 R
)(Duty Cycle) =
DS,ON
(14/2)2(0.037*)(3.3+0.4)/(5+0.4-0.35) = 1.3W/FET
* Note: R
25°C. R
using a single MOSFET. When using two MOSFETs in parallel, the
temperature effects should not cause the R
listed maximum value of 37mΩ.
increases with temperature. Assume R
DS,ON
can easily increase to 50mΩ at high temperature when
DS,ON
DS,ON
DS,ON
to rise above the
• Less heat sink required.
With power dissipation down to around one watt and with
MOSFETs mounted flat on the motherboard, considerable
less heat sink is required. The junction-to-case thermal
resistance for the MOSFET package (TO-220) is typically
at 2°C/W and the motherboard serves as an excellent heat
sink.
• Higher current capability.
With thermal management under control, this on-board
DC-DC converter is able to deliver load currents up to
14.5A with no performance or reliability concerns.
MOSFET Gate Bias
MOSFET can be biased by one of two methods: Charge
Pump and 12V Gate Bias.
• Method 1. Charge pump (or Boostrap) method.
Figure 5 employs a charge pump to provide gate bias.
Capacitor CP is the charge pump deployed to boost the
voltage of the RC5050 output driver. When the MOSFET
switches off, the source of the MOSFET is at -0.6V.
VCCQP is charged through the Schottky diode to 4.5V.
Thus, the capacitor CP is charged to 5V. When the MOSFET turns on, the source of the MOSFET voltage is equal
to 5V. The capacitor voltage follows, and hence provides a
voltage at VCCQP equal to 10V. The Schottky diode is
required to provide the charge path when the MOSFET is
off, and reverses bias when the VCCQP goes to 10V. The
charge pump capacitor, CP, needs to be a high Q, high frequency capacitor. A 1µF ceramic capacitor capacitor is
recommended here.
= 25mΩ at
+5V
DS2
PWM/PFM
Control
VCCQP
HIDRV
CP
M1
DS1
L1
RS
VO
CB
65-AP50-01
Figure 5. Charge Pump Configuration
• Method 2. 12V Gate Bias.
Figure 6 illustrates how a 12V source can be used to bias
the VCCQP. A 47 Ω resistor is used to limit the transient
current into the VCCQP pin and a 1µF capacitor filter is
used to filter the VCCQP supply. This method provides a
higher gate bias voltage (VGS) to the MOSFET, and therefore reduces the R
of the MOSFET and reduces the
DS,ON
power loss due to the MOSFET. Figure 7 shows how
R
reduces dramatically with VGS increases. A 6.2V
DS,ON
Zener diode (D1) is placed to clamp the voltage at VCCQP
to a maximum of 12V and ensure that the absolute maximum voltage of the IC will not be exceeded
+5V
47Ω
+12V
D1
1µF
6.2V
M1
L1
RS
DS1
R(DS)Fuji
R(DS)7060
R(DS)706A
R(DS)-706AEL
(V)
GS
VO
CB
65-AP50-02
0.1
0.09
0.08
0.07
0.06
(Ω)
0.05
DS,ON
0.04
R
0.03
0.02
0.01
VCCQP
HIDRV
PWM/PFM
Control
Figure 6. 12V Gate Bias Configuration
0
1.5 2 2.5 3 3.5 4 5 6 7 8 9 10 11
Gate-Source Voltage, V
Figure 7. R
vs. VGS for Selected MOSFETs
DS,ON
8
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