Fairchild RC5042, RC5040 User Manual

Application Note 42

Implementing the RC5040 and RC5042
DC-DC Converters on Pentium

®

Pro Motherboards

www.fairchildsemi.com

Introduction

This document describes how to implement a switching volt­age regulator using an RC5040 or an RC5042 high speed
controller, a power inductor, a Schottky diode, appropriate
capacitors, and external power MOSFETs. This regulator
forms a step down DC-DC converter that can deliver up to

14.5A of continuous load current at voltages ranging from

2.1V to 3.5V. A specific application circuit, design consider­ations, component selection, PCB layout guidelines and per­formance evaluation procedures are covered in detail.

In the past 10 years, microprocessors have ev olved at such an
exponential rate that a modern chip can rival the computing
power of a mainframe computer. Such evolution has been
possible because of the increasing numbers of transistors that
processors integrate. Pentium CPUs, for example, integrate
well over 5 million transistors on a single piece of silicon.

To integrate so many transistors on a piece of silicon, their
physical geometry has been reduced to the sub-micron level.
As a result of each geometry reduction, the corresponding
operational voltage for each transistor has also been reduced.
This changing voltage for the CPU demands the design of a
programmable power supply—a design that is not com­pletely re-engineered with every change in CPU voltage.

The operational voltage of CPUs has shown a downwards
trend for the past 5 years: from 5V for the x386 and x486, to

3.3V for Pentium, and 3.1V for Pentium Pro. Furthermore,
emerging chip technologies may require operating voltages
as low as 2.5V. With this trend in mind, Raytheon Electron­ics has designed the RC5040 and RC5042 controllers. These
controllers integrate the necessary programmability to
address the changing power supply requirements of lower
voltage CPUs.

Previous generations of DC-DC converter controllers were
designed with fixed output voltages adjustable only with a
set of external resistors. In a high volume production envi­ronment (such as with personal computers), however, a CPU
voltage change requires a CPU board re-design to accommo­date the new voltage requirement. The integrated 4-bit DAC
in the RC5040 and the RC5042 reads the voltage ID code
from the Pentium Pro microprocessor and configures the sys­tem to provide the appropriate voltage. In this manner, the
PC board does not have to be re-designed each time the CPU
voltage changes. The CPU can thus automatically configure
its own required voltage.

Pentium Pro and OverDrive®
Processor Power Requirements

Use Intel’s AP-523 Application Note, Pentium® Pro
Processor Power Distribution Guidelines, November 1995

(order number 242764-001), as a basic reference. The speci­fications contained in this document have been modified
slightly from the original Intel document to include updated
specifications for Pentium Pro microprocessors. Please con­tact Intel Corporation for specific details.

Input V oltages

Available inputs are +5V ±5% and +12V ±5%. Raytheon
Electronics’ DC-DC converters may use either or both
inputs. Their input voltage requirements are listed in Table 1.

Table 1. Input Voltage Requirements

Controller

Part #

RC5040
RC5042

RC5043 +5V ±5% 12V ±5% 12V ±5%

V

CC

+5V ±5% +5V ±5% +5V ±5% or

Pentium Pro DC Power Requirements

Refer to Table 2 for the power supply specifications for
Pentium Pro and Overdrive Processors. For a motherboard
design without a standard Voltage Regulator Module (VRM)
socket, the on-board DC-DC converter must supply a mini­mum ICCP current of 13.9A at 2.5V and 12.4A at 3.3V. For a
flexible motherboard design, the on-board converter must be
able to supply 14.5A maximum ICCP.

DC V oltage Regulation

As indicated in Table 2, the voltage level supplied to the
CPU must be within ±5% of its nominal setting. Voltage
regulation limits must include:

• Output load ranges specified in Table 2

• Output ripple/noise

• DC output initial voltage set point

• Temperature and w arm up drift (Ambient +10°C to +60°C
at full load with a maximum rate of change of 5°C per 10
minutes minimum but no more than 10°C per hour)

• Output load transient with:
Slew rate >30A/µs at the converter pins
Range: 0.3A – ICCP Max (as defined in Table 2).

MOSFET

Drain

MOSFET

Gate Bias

12V ±5%

Rev. 1.1.0

AN42 APPLICATION NOTE

Table 2. Intel Pentium Pro and OverDrive Processor Power Specifications

Voltage

Specification

CPU Model & Features

150MHz – 256K L2 Cache 3.1 ± 5% 9.9 29.2
166MHz – 512K L2 Cache 3.3 ± 5% 11.2 35.0
180MHz – 256K L2 Cache 3.3 ± 5% 10.1 31.7
200MHz – 256K L2 Cache 3.3 ± 5% 11.2 35.0
200MHz – 512K L2 Cache 3.3 ± 5% 12.4 37.9

OverDrive Processors

150 MHz 2.5 ± 5% 11.2 26.7
180 MHz 12.5 29.7
200 MHz 13.9 32.9

Flexible Motherboard

Notes:

1. Maximum power values are measured at typical V

2. Flexible motherboard specifications are recommendations only. Actual specifications are subject to change.

2

VCCP (VDC)

2.4-3.5 ± 5% 14.5 45.0

P to take into account the thermal time constant of the CPU package.

CC

Maximum

Current

ICCP (A)

Maximum Thermal

Design Power

(W)

1

Output Ripple and Noise

Ripple and noise are defined as periodic or random signals
over the frequency band of 20MHz at the output pins. Output
ripple and noise requirements of ±1.0% must be met
throughout the full load range and under all specified input
voltage conditions.

Efficiency

The efficiency of the DC-DC converter must be greater
than 80% at high current draw and greater than 40% at low
current draw.

Processor Voltage Identification

The Pentium Pro package has four voltage identification
pins, VID3–VID0, that can be used for automatic selection
of the power supply voltage. These pins are internally uncon­nected or are shorted to ground (VSS). The logic status of the
pins defines the voltage required by the processor. The VID
codes have been implemented to support voltage specifica­tion variations on future Pentium Pro processors. These
codes are presented in Table 3. A ‘1’ refers to an open pin
and a ‘0’ refers to a short to ground. The VCCP power supply
should supply the voltage that is requested or disable itself.

Table 3. Voltage Identification Codes for Pentium Pro

Data Bits V

VID3 VID2 VID1 VID0 (VDC)

1 1 1 1 No CPU
1 1 1 0 2.1
1 1 0 1 2.2
1 1 0 0 2.3
1 0 1 1 2.4
1 0 1 0 2.5
1 0 0 1 2.6
1 0 0 0 2.7
0 1 1 1 2.8
0 1 1 0 2.9
0 1 0 1 3.0
0 1 0 0 3.1
0 0 1 1 3.2
0 0 1 0 3.3
0 0 0 1 3.4
0 0 0 0 3.5

CC

P

I/O Controls

In addition to the voltage identification pins, several signals
exist to control the DC-DC converter or to provide feedback
from the converter to the CPU. These are Power-Good
(PWRGD), Output Enable (OUTEN), and Upgrade Present
(UP). These signals are discussed later.

2

APPLICATION NOTE AN42

I

L

VINV

OUT

–( )T

ON

L1

-----------------------------------------------=

V

OUT

V

IN

T

ON

T

S

-----------

 

 

=

RC5040 and RC5042 Description

Simple Step-Down Converter

S1

V

IN

Figure 1. Simple Buck DC-DC Converter

Figure 1 illustrates a step-down DC-DC converter with no
feedback control. The basic step-down converter serves as
the basis for deriving the design equations for the RC5040
and RC5042. From Figure 1, the basic operation begins by
closing the switch S1, so that the input voltage VIN is
impressed across inductor L1. The current flowing through
this inductor is given by the following equation:

where T

is the duty cycle (the time when S1 is closed).

ON

When S1 opens, the diode D1 conducts the inductor
current and the output current is delivered to the load accord­ing to the following equation:

V

OUTTSTON

--------------------------------------------=

I

L

–( )

L1

where TS is the overall switching period and (TS – TON) is
the time during which S1 is open.

By solving these equations you can obtain the basic relation­ship for the output voltage of a step-down converter:

D1

L1

+

C1 RL Vout

–

65-AP42-01

The RC5040 and RC5042 Controllers

The RC5040 is a programmable synchronous-mode DC-DC
converter controller. The RC5042 is a non-synchronous ver­sion of the RC5040. When designed with the appropriate
external components, either device can be configured to
deliver more than 14.5A of output current. During heavy
loading conditions, these controllers function as current­mode PWM step-down regulators. Under light loads, they
function in PFM (pulse frequency modulation) or pulse skip­ping mode. The controllers sense the load level and switch
between the two operating modes automatically, thus opti­mizing efficiency under all loads. The key differences
between the RC5040 and RC5042 are listed in Table 4.

Table 4. RC5040 and RC5042 Differences

RC5040 RC5042

Operation Synchronous Non-Synchronous
Package 20-pin SOIC 16-pin SOIC
Output Enable/

Disable

Refer to the RC5040 Block Diagram illustrated in Figure 2.
The control loop of the regulator contains two main sections:
the analog control block and the digital control block. The
analog block consists of signal conditioning amplifiers feed­ing into a set of comparators which provide the inputs to the
digital block. The signal conditioning section accepts inputs
from the IFB (current feedback) and VFB (voltage feedback)
pins and sets two controlling signal paths. The voltage con­trol path amplifies the VFB signal and presents the output to
one of the summing amplifier inputs. The current control
path takes the difference between the IFB and VFB and pre­sents the result to another input of the summing amplifier.
These two signals are then summed together with the slope
compensation input from the oscillator. This output is then
presented to a comparator, which provides the main PWM
control signal to the digital control block.

Yes No

In order to obtain a more accurate approximation for V
we must also include the forward voltage VD across diode
D1 and the switching loss, VSW. After taking into account
these factors, the new relationship becomes:

T

ON

-----------

V

OUT

Where VSW = IL • R

VINVDVSW–+( )

.

DS,ON

V

–=

T

D

S

OUT

The additional comparators in the analog control section sets
the threshold for when the RC5040 enters PFM mode during

,

light loads and the point when the current limit comparator
disables the output drive signals to the MOSFETs.

The digital control block is designed to take the comparator
inputs along with the main clock signal from the oscillator
and provide the appropriate pulses to the HIDRV and
LODRV pins that control the external power MOSFETs. The
digital section was designed utilizing high speed Schottky
transistor logic, thus allowing the RC5040 to operate at clock
speeds as high as 1MHz.

3

AN42 APPLICATION NOTE

Main Control Loop

OSCILLATOR

–
+

VREF

4-BIT

DAC

VID0
VID1
VID2
VID3

1.24V

REFERENCE

Figure 2. RC5040 Block Diagram

High Current Output Drivers

The RC5040 contains two identical high current output
drivers that use high speed bipolar transistors in a push-pull
configuration. Each driver is capable of deliv ering 1A of cur­rent in less than 100ns. Each driver’s power and ground are
separated from the chip power and ground for additional
switching noise immunity. The HIDRV driver’s power sup­ply, VCCQP, is boot-strapped from a flying capacitor as
illustrated in Figure 3. Using this configuration, C12 is
charged from VCC via the Schottky diode DS2 and boosted
when the FET is turned on. This scheme provides a VCCQP
voltage equal to 2•VCC – VDS(DS2), or approximately 9.5V
when VCC = 5V. This voltage is sufficient to provide the 9V
gate drive to the MOSFET that is required to achieve a low

DS(ON). Since the low side synchronous FET is referenced to

R
ground (see Figure 4), boosting the gate drive voltage is not
needed and the VCCP power pin can be tied to VCC.
Refer to Typical Operating Characteristics of the RC5040
data sheet for a full load VCCQP waveform.

Internal Voltage Reference

The reference used in the RC5040 is a precision band-gap
voltage reference, with internal resistors precisely trimmed
to provide a near zero temperature coefficient, TC. Added to
the reference voltage is the output from a 4-bit DAC. The
DAC is provided meet Pentium Pro specifications, requiring
a programmable converter output via a 4-bit voltage identifi­cation (VID) code. This code scales the output voltage from

2.0V (no CPU) to 3.5V in 100mV increments. To guarantee
stable operation under all loads, a 10KΩ pull-up resistor and

0.1µF of decoupling capacitance should be connected to the
VREF pin. No load should be imposed on this pin.

RC5040

–
+

–
+

–
+

DIGITAL

CONTROL

POWER

GOOD

PWRGD

+5V
VIN

VO

65-5040-01

Power Good (PWRGD)

The RC5040 and RC5042 Power Good function has been
designed according to Intel’s Pentium Pro DC-DC converter
specification. The Power Good function provides a constant
voltage monitor on the VFB pin. The internal circuitry of the
converter compares the VFB signal to the VREF voltage and
outputs an active-low interrupt signal to the CPU when the
power supply voltage exceeds ±7% of its nominal setpoint.
The Power Good flag provides no other control function to
the RC5040.

Output Enable (OUTEN)

Intel specifications state that the DC-DC converter should
accept an open collector signal for controlling the output
voltage. A logic LOW for this signal disables the output volt­age. When disabled, the PWRGD output is in the low state.
This feature is available for the RC5040 only.

Upgrade Present (UP#)

Intel specifications state that the DC-DC converter must
accept an open collector signal that indicates the presence of
an upgrade processor. The typical state is high (for a stan­dard P6 processor). When the signal is low or in theground
state (for the OverDrive processor), the output voltage must
be disabled unless the converter can supply the OverDrive
processor’s power requirements. When disabled, the
PWRGD output must be in the low state. Because the
RC5040 and RC5042 can supply the OverDrive processor
requirements, the UP# signal is not required.

4

APPLICATION NOTE AN42

Over-Voltage Protection

The RC5040 and RC5042 constantly monitor the output
voltage for protection against over voltage. If the voltage at
the VFB pin exceeds 20% of the selected program voltage,
an over-voltage condition is assumed, and the controller dis­ables the output drive signal to the external MOSFET(s).

Short Circuit Protection

A current sense methodology is implemented to disable the
output drive signal to the MOSFET(s) when an over-current
condition is detected. The voltage drop created by the output
current flowing across a sense resistor is presented to an
internal comparator. When the voltage developed across the
sense resistor exceeds the comparator threshold voltage,
the controller disables the output drive signal to the
MOSFET(s).

The DC-DC converter returns to normal operation after the
fault has been removed, for either an over voltage or a short
circuit condition.

Oscillator

The RC5040 oscillator section is implemented using a
fixed current capacitor charging configuration. An external
capacitor (CEXT) is used to preset the oscillator frequency
between 200KHz and 1MHz. This allows maximum flexibil­ity in setting the switching frequency and in choosing exter­nal components.

In general, a lower operating frequency increases the peak
ripple current flowing through the output inductor, allowing
the use of a larger inductor value. Operation at lower fre­quencies increases the amount of energy storage that the
bulk output capacitors must provide during load transients
that occur due to the slower loop response of the controller.

In addition, note that the efficiency losses due to switching
are relatively fixed per switching cycle. Therefore, as the
switching frequency increases, the contribution toward effi­ciency due to switching losses also increases.

RC5040 has an optimal operating frequency of 650KHz.
This frequency allows the use of smaller inductive and
capacitive components while optimizing peak efficiency
under all operating conditions.

Design Considerations and
Component Selection

Application Circuits

Figure 3 illustrates a typical non-synchronous application
using the RC5040. Figure 4 shows a typical synchronous
application using the RC5040, and Figure 5 shows a typical
non-synchronous application using the RC5042.

VREF

GND

VCC

C4

0.1µF

R7

10K

C7

0.1µF

L2

2.6µH

VID3
VID2
VID1
VID0

OUTEN

C1

1000µF

C2

1000µF

12
13
14
15
16
17
18
19
20

R1
R2
R3
R4

C3

1000µF

RC5040

C

39pF

10K
10K
10K
10K

EXT

C5

0.1µF

1011

9
8
7
6
5
4
3
2
1

C10

0.1µF

R5

10K

C6

4.7µF

VCC

DS2

1N5817

C12
1µF

2SK1388

R6

10K

M1

C11

0.22µF

C8

0.1µF

DS1

MBR1545CT

VCC

PWRGD

C9

0.1µF

M2
2SK1388

L1

1.3µH

R

SENSE

8mΩ

F

µ

1500

C13

65-AP42-03

1500µF

C14

F

µ

1500

C15

VO

Figure 3. Non-Synchronous DC-DC Converter Application Schematic Using RC5040

5

AN42 APPLICATION NOTE

VREF

GND

VCC

C4

0.1µF

R7

10K

C7

0.1µF

VID3
VID2
VID1
VID0

OUTEN

L2

2.6µH

C1

1000µF

12
13
14
15
16
17
18
19
20

R1
R2
R3

R4

C2

1000µF

RC5040

C
39pF

10K
10K
10K
10K

EXT

C3

1000µF

1011

9
8
7
6
5
4
3
2
1

C10

0.1µF

C5

0.1µF

R5

10K

C6

4.7µF

VCC

DS2

1N5817

C12

1µF

2SK1388

2SK1388

M3

R6

10K

M1

0.22µF

C11

C8

0.1µF

1N5817

VCC

PWRGD

DS1

C9

0.1µF

M2
2SK1388

L1

1.3µH

R

SENSE

8mΩ

65-AP42-04

1500µF

C13

1500µF

C14

VO

1500µF

C15

Figure 4. Synchronous DC-DC Converter Application Schematic Using RC5040

VCC

0.1µF

VREF

GND

L2

2.6µH

C4

C1

1000µF

R7
10K

C7

0.1µF

VID3

VID2
VID1
VID0

9
10
11
12
13
14
15
16

R1

R2
R3
R4

RC5042

C3

C2
1000µF 1000µF

8
7

4

2
1

C

EXT

39pF

10K
10K
10K
10K

C10

C5

0.1µF
DS2

1N5817

C12

6
5

C6

4.7µF

1µF

M1

2SK1388

3

R6

10K

C8

0.1µF

DS1

MBR1545CT

VCC

C9

0.1µF

M2
2SK1388

L1

1.3µH

R

SENSE

8mΩ

F

µ

1500

C13

65-AP42-05

1500µF

C14

VO

1500µF

C15

PWRGD

VCC

C11

0.22µF

0.1µF

Figure 5. Non-Synchronous DC-DC Converter Application Schematic Using RC5042

6

APPLICATION NOTE AN42

MOSFET Selection

This application requires the use of N-channel, Logic Level
Enhancement Mode Field Effect Transistors. The desired
characteristics of these components are:

• Low Static Drain-Source On-Resistance
R

• Low gate drive voltage, VGS ≤ 4.5V

Table 5. MOSFET Selection Table

Manufacturer & Model # Conditions

Fuji
2SK1388

Siliconix
SI4410DY

National Semiconductor
NDP706AL

< 37 mΩ (lower is better)

DS,ON

V

= 4V

GS

ID = 17.5A
V

= 4.5V

GS

ID = 5A
V

= 5V

GS

ID = 40A

• Power package with low thermal resistance

• Drain current rating of 20A minimum

• Drain-Source voltage > 15V.

The on-resistance (R

) is the main parameter for MOS-

DS,ON

FET selection. It determines the MOSFET’s power dissipa­tion, thus significantly affecting the efficiency of the
converter. Several suitable MOSFETs are shown in Table 5.

R

1

DS, ON

(mΩ)

Package

TJ = 25°C 25 37 TO-220 Φ
TJ = 125°C 37 —
TJ = 25°C 16.5 20 SO-8
TJ = 125°C 28 34

(SMD)

TJ = 25°C 13 15 TO-220 Φ

NDP706AEL TJ = 125°C 20 24
National Semiconductor V
NDP603AL TJ = 125°C 42 54 Φ
National Semiconductor V
NDP606AL TJ = 125°C 33 40 Φ
Motorola V
MTB75N03HDL TJ = 125°C 9.3 14 (D2 PAK) Φ
Int. Rectifier V
IRLZ44 TJ = 125°C — 46 Φ
Int. Rectifier V
IRL3103S TJ = 125°C 31 Φ

Note:

1. R

turers and are approximations only.

) values at Tj = 125°C for most devices were extrapolated from the typical operating curves supplied by the manufac-

DS(ON

= 4.5V

GS

ID = 10A

= 5V

GS

ID = 24A

= 5V

GS

ID = 37.5A

= 5V

GS

ID = 31A

= 4.5V

GS

ID = 28A

TJ = 25°C 31 40 TO-220 Φ

TJ = 25°C 22 25 TO-220 Φ

TJ = 25°C 6 9 TO-263 Φ

TJ = 25°C — 28 TO-220 Φ

TJ = 25°C — 19 TO-220 Φ

Thermal

ResistanceTyp. Max.

= 75

JA

Φ

= 50

JA

= 62.5

JA

Φ

= 1.5

JC

= 62.5

JA

= 2.5

JC

= 62.5

JA

= 1.5

JC

= 62.5

JA

= 1.0

JC

= 62.5

JA

= 1.0

JC

= 62.5

JA

= 1.0

JC

Two MOSFETs in Parallel

We recommend two MOSFETs used in parallel instead of a
single MOSFET. The following significant advantages are
realized using two MOSFETs in parallel:

• Significant reduction of power dissipation.
Maximum current of 14A with one MOSFET:
P

MOSFET

(14)2(0.050*)(3.3+0.4)/(5+0.4-0.35) = 7.2 W
With two MOSFETs in parallel:

P

MOSFET

(14/2)

* Note: R

= (I2 R

= (I2 R

2

(0.037*)(3.3+0.4)/(5+0.4-0.35) = 1.3W/FET

increases with temperature. Assume R

DS,ON

at 25°C. R
when using a single MOSFET. When using two MOSFETs in
parallel, the temperature effects should not cause the R
above the listed maximum value of 37mΩ.

DS,ON

)(Duty Cycle) =

DS,ON

)(Duty Cycle) =

DS,ON

can easily increase to 50mΩ at high temperature

DS,ON

DS,ON

= 25mΩ

to rise

• No added heat sink required.

With the power dissipation down to around one watt and
with MOSFETs mounted flat on the motherboard, no
external heat sink is required. The junction-to-case
thermal resistance for the MOSFET package (TO-220) is
typically at 2°C/W and the motherboard serves as an
excellent heat sink.

• Higher current capability.

With thermal management under control, this on-board
DC-DC converter can deliver load currents up to 14.5A
with no performance or reliability concerns.

7

AN42 APPLICATION NOTE

MOSFET Gate Bias

The MOSFET(s) can be biased using one of two methods:
Charge Pump or 12V Gate Bias.

Charge Pump (or Bootstrap)

Figure 6 employs a charge pump to provide the MOSFET
gate bias. The charge pump capacitor, CP, is used as a flying
capacitor to boost the voltage of the RC5040 or RC5042 out­put driver . When the MOSFET switches off, the source of the
MOSFET is at -0.6V. VCCQP is charged through the Schot­tky diode to 4.5V. Thus, the capacitor CP is charged to 5V.
When the MOSFET turns on, the source of the MOSFET is
at approximately 5V. The capacitor voltage follows, and
hence provides a voltage at VCCQP equal to 10V. The Schot­tky is required to provide the charge path when the MOSFET
is off, and then reverses bias when the VCCQP goes to 10V.
The capacitor CP needs to be a high Q and high frequency
capacitor. A 1µF ceramic capacitor is recommended here.

+5V

DS2

VCCQP

HIDRV

PWM/PFM

Control

CP

M1

DS1

L1

RS

CB

VO

12V Gate Bias

Figure 7 illustrates how an external 12V source can be used
to bias VCCQP. A 47 Ω resistor is used to limit the transient
current into the VCCQP pin, and a 1µF capacitor filter is
used to filter the VCCQP supply. This method provides a
higher gate bias voltage (VGS) to the MOSFET, and there­fore reduces the R
MOSFET . Figure 8 illustrates how R

and resulting power loss within the

DS,ON

decreases dra-

DS,ON

matically as VGS increases. A 6.2V Zener (DS2) is used to
clamp the voltage at V

to a maximum of 12V and

CCQP

ensure that the absolute maximum voltage of the IC is not
exceeded.

Warning: The 12V Gate Bias method applies only to the
RC5042. The RC5040 has not been designed to accept an
external 12V gate bias voltage, and may be damaged if
this method is used.

+5V

VCCQP

HIDRV

47Ω

D1

6.2V

M1

DS1

L1

RS

VO

CB

PWM/PFM

Control

+12V

Figure 6. Charge Pump Configuration

0.1

0.09

0.08

0.07

(Ω)

0.06

0.05

0.04

DS,ON

R

0.03

0.02

0.01
0

1.5 2 2.5 3 3.5 4 5 6 7 8 9 10 11

Figure 8. R

65-AP42-06

Gate-Source Voltage, V

vs. VGS for Selected MOSFETs

DS,ON

GS

65-AP42-07

Figure 7. 12V Gate Bias Configuration

R(DS)Fuji
R(DS)Fuji
R(DS)706A
R(DS)-706AEL

(V)

8