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MM74HC157
Quad 2-Input Multiplexer
MM74HC157 Quad 2-Input Multiplexer
September 1983
Revised February 1999
General Description
The MM74HC157 high speed Quad 2-to-1 Line data selector/Multiplexers utilizes advanced silicon-gate CMOS technology. It possesses the high noise immunity and low
power consumption of standard CMO S integrated circuits,
as well as the ability to drive 10 LS-TTL loads.
This device consists of four 2-input digital multiplexers with
common select and STROB E inputs. When the STROBE
input is at logical “0” the four outputs assume the values as
selected from the inputs. W hen the STROBE input is at a
logical “1” the outputs assume logical “0”.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by internal diode clamps to V
and ground.
CC
Features
■ Typical propagation delay: 14 ns data to any output
■ Wide power supply range: 2–6V
■ Low power supply quiescen t current: 80 µA maximum
(74HC Series)
■ Fan-out of 10 LS-TTL loads
■ Low input current: 1 µA maximum
Ordering Code:
Order Number Package Number Package Description
MM74HC157M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC157SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC157MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC157N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Function Table
Inputs Output
Strobe Select A B Y
HXXXL
LLLXL
LLHXH
LHXLL
LHXHH
H = HIGH Level,
L = LOW Level
X = Irrelevant
Top View
© 1999 Fairchild Semiconductor Corporation DS005314.prf www.fairchildsemi.com
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Logic Diagram
MM74HC157
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Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
DC Output Voltage (V
Clamp Diode Current (I
DC Output Current, per pin (I
or GND Current, per pin (ICC) ±50 mA
DC V
CC
Storage Temperature Range (T
Power Dissipation (P
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds ) 260°C
) −1.5 to V
IN
) −0.5 to V
OUT
, IOK) ±20 mA
IK
) ±25 mA
OUT
) −65°C to +150°C
STG
)
D
)
L
CC
CC
Recommended Operating
Conditions
+1.5V
Supply Voltage (V
+0.5V
DC Input or Output Voltage 0 V
, V
(V
IN
OUT
Operating Temperature Range (T
Input Rise or Fall Times
, tf) V
(t
r
CC
V
CC
V
Note 1: Absolute Maximum Ra tings are those valu es beyond w hich damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
CC
)26V
CC
)
) −40 +85 °C
A
= 2.0V 1000 ns
= 4.5V 500 ns
= 6.0V 400 ns
Min Max Units
CC
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions
V
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
V
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage 4.5V 1.35 1.35 1.35 V
V
Minimum HIGH Level V
OH
Output Voltage |I
V
Maximum LOW Level V
OL
Output Voltage |I
I
Maximum Input V
IN
Current
I
Maximum Quiescent V
CC
Supply Current I
Note 4: For a powe r supply o f 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4. 5V valu es shou ld be u sed when
designing with this supply. Worst case V
, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6. 0V values should be us ed.
rent (I
IN
= VIH or V
IN
OUT
V
IN
|I
OUT
|I
OUT
IN
OUT
V
IN
|I
OUT
|I
OUT
IN
IN
OUT
and VIL occur at V
IH
IL
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
= VIH or V
IL
| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
= VIH or V
IL
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
= VIH or V
IL
| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
= VCC or GND 6.0V 8.0 80 160 µA
= 0 µA
CC
V
CC
6.0V 4.2 4.2 4.2 V
6.0V 1.8 1.8 1.8 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3 .8 5V.) The worst c as e leakage cur-
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Typ Guaranteed Limits
MM74HC157
V
Units
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AC Electrical Characteristics
V
= 5V, TA = 25°C, CL = 15 pF, tr = t
CC
= 6 ns
f
Symbol Parameter Conditions Typ
t
, t
PHL
PLH
MM74HC157
t
, t
PHL
PLH
Maximum Propagation 14 20 ns
Delay, Data to Output
Maximum Propagation 14 20 ns
Delay, Select to Output
t
PHL
, t
PLH
Maximum Propagation 12 18 ns
Delay, Strobe to Output
AC Electrical Characteristics
C
= 50 pF, tr = t
L
Symbol Parameter Conditions
t
, t
PHL
PLH
t
, t
PHL
PLH
t
, t
PHL
PLH
t
, t
TLH
THL
C
IN
C
PD
Note 5: CPD determines the no lo ad dynamic power con s um ption, PD = CPD V
= CPD VCC f + ICC.
I
S
= 6 ns (unless otherwise specified)
f
V
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Typ Guaranteed Limits
Maximum Propagation 2.0V 63 125 158 186 ns
Delay, Data to Output 4.5V 13 25 32 37 ns
6.0V 11 21 27 32 ns
Maximum Propagation 2.0V 63 125 158 186 ns
Delay, Select to Output 4.5V 13 25 32 37 ns
6.0V 11 21 27 32 ns
Maximum Propagation 2.0V 58 115 145 171 ns
Delay, Strobe to Output 4.5V 12 23 29 34 ns
6.0V 10 20 25 29 ns
Maximum Output Rise 2.0V 30 75 95 110 ns
and Fall Time 4.5V 8 15 19 22 ns
6.0V 7 13 16 19 ns
Maximum Input 5 10 10 10 pF
Capacitance
Power Dissipation (per 57 pF
Capacitance (Note 5) Multiplexer)
2
f + ICC VCC, and the no load dynamic current consu m pt ion,
CC
Guaranteed
Limit
Units
Units
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Physical Dimensions inches (millimeters) unless otherwise noted
MM74HC157
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16A
Package Number M16D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
MM74HC157
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
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Package Number MTC16
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
MM74HC157 Quad 2-Input Multiplexer
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re asonably expected to result in a significant injury to the
user.
Package Number N16E
2. A critical componen t in any com ponen t of a life s upport
device or system whose failu re to perform can b e reasonably expected to cause the failure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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