FAIRCHILD MM74HC04 Datasheet
MM74HC04
Hex Inverte r
MM74HC04 Hex Inverter
September 1983
Revised February 1999
General Description
The MM74HC04 inverters utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low p ower con sum ption of standa rd
CMOS integrated circuits.
The MM74HC04 is a triple buffered inverter. It has high
noise immunity and the ability to drive 10 LS-TTL loads.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by internal diode clamps to V
and ground.
CC
Features
■ Typical propagation delay: 8 ns
■ Fan out of 10 LS-TTL loads
■ Quiescent power consumption: 10 µW maximum at
room temperature
■ Low input current: 1 µA maximum
Ordering Code:
Order Number Package Number Package Description
MM74HC04M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC04SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.5mm Wide
MM74HC04MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC04N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Logic Diagram
1 of 6 Inverter s
Top View
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Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
MM74HC04
DC Output Voltage (V
Clamp Diode Current (I
DC Output Current, per pin (I
or GND Current, per pin (ICC) ±50 mA
DC V
CC
Storage Temperature Range (T
Power Dissipation (P
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds ) 260°C
) −1.5 to V
IN
) −0.5 to V
OUT
, IOK) ±20 mA
IK
) ±25 mA
OUT
) −65°C to +150°C
STG
)
D
)
L
CC
CC
Recommended Operating
Conditions
+1.5V
+0.5V
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
, V
(V
Operating Temperature Range (T
)
IN
OUT
) −40 +85 °C
A
Input Rise or Fall Times
, tf) V
(t
r
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are refe renced to ground.
Note 3: Power Dissipation tem perature de rating — pla stic “N” pac kage: −
12 mW/°C from 65 °C to 85°C.
= 2.0V 1000 ns
CC
= 4.5V 500 ns
V
CC
= 6.0V 400 ns
V
CC
Min Max Units
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions
V
V
V
V
I
I
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage 4.5V 1.35 1.35 1.35 V
Minimum HIGH Level V
OH
Output Voltage |I
Maximum LOW Level VIN = V
OL
Output Voltage |I
Maximum Input V
IN
Current
Maximum Quiescent V
CC
Supply Current I
Note 4: For a power supp ly of 5V ±1 0% the worst c ase ou tput volta ges (VOH, and VOL) occur for HC at 4.5V. Thus the 4. 5V valu es shoul d be use d when
designing with this supply. Worst case V
, ICC, and IOZ) occur for CMOS at the higher voltage and s o th e 6.0V values should be used.
(I
IN
= V
IN
IL
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
OUT
V
= V
IN
IL
|I
| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
OUT
|I
| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
OUT
IH
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
OUT
V
= V
IN
IH
|I
| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
OUT
|I
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
OUT
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
IN
= VCC or GND 6.0V 2.0 20 40 µA
IN
= 0 µA
OUT
and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current
IH
V
CC
6.0V 4.2 4.2 4.2 V
6.0V 1.8 1.8 1.8 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Typ Guaranteed Limits
CC
V
Units
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