MM74HC04
Hex Inverte r
MM74HC04 Hex Inverter
September 1983
Revised February 1999
General Description
The MM74HC04 inverters utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low p ower con sum ption of standa rd
CMOS integrated circuits.
The MM74HC04 is a triple buffered inverter. It has high
noise immunity and the ability to drive 10 LS-TTL loads.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by internal diode clamps to V
and ground.
CC
Features
■ Typical propagation delay: 8 ns
■ Fan out of 10 LS-TTL loads
■ Quiescent power consumption: 10 µW maximum at
room temperature
■ Low input current: 1 µA maximum
Ordering Code:
Order Number Package Number Package Description
MM74HC04M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC04SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.5mm Wide
MM74HC04MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC04N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Logic Diagram
1 of 6 Inverter s
Top View
© 1999 Fairchild Semiconductor Corporation DS005069.prf www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
MM74HC04
DC Output Voltage (V
Clamp Diode Current (I
DC Output Current, per pin (I
or GND Current, per pin (ICC) ±50 mA
DC V
CC
Storage Temperature Range (T
Power Dissipation (P
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds ) 260°C
) −1.5 to V
IN
) −0.5 to V
OUT
, IOK) ±20 mA
IK
) ±25 mA
OUT
) −65°C to +150°C
STG
)
D
)
L
CC
CC
Recommended Operating
Conditions
+1.5V
+0.5V
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
, V
(V
Operating Temperature Range (T
)
IN
OUT
) −40 +85 °C
A
Input Rise or Fall Times
, tf) V
(t
r
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are refe renced to ground.
Note 3: Power Dissipation tem perature de rating — pla stic “N” pac kage: −
12 mW/°C from 65 °C to 85°C.
= 2.0V 1000 ns
CC
= 4.5V 500 ns
V
CC
= 6.0V 400 ns
V
CC
Min Max Units
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions
V
V
V
V
I
I
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage 4.5V 1.35 1.35 1.35 V
Minimum HIGH Level V
OH
Output Voltage |I
Maximum LOW Level VIN = V
OL
Output Voltage |I
Maximum Input V
IN
Current
Maximum Quiescent V
CC
Supply Current I
Note 4: For a power supp ly of 5V ±1 0% the worst c ase ou tput volta ges (VOH, and VOL) occur for HC at 4.5V. Thus the 4. 5V valu es shoul d be use d when
designing with this supply. Worst case V
, ICC, and IOZ) occur for CMOS at the higher voltage and s o th e 6.0V values should be used.
(I
IN
= V
IN
IL
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
OUT
V
= V
IN
IL
|I
| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
OUT
|I
| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
OUT
IH
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
OUT
V
= V
IN
IH
|I
| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
OUT
|I
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
OUT
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
IN
= VCC or GND 6.0V 2.0 20 40 µA
IN
= 0 µA
OUT
and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current
IH
V
CC
6.0V 4.2 4.2 4.2 V
6.0V 1.8 1.8 1.8 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Typ Guaranteed Limits
CC
V
Units
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AC Electrical Characteristics
V
= 5V, TA = 25°C, CL = 15 pF, tr = t
CC
= 6 ns
f
Symbol Parameter Conditions Typ
t
, t
PHL
Maximum Propagation 8 15 ns
PLH
Delay
AC Electrical Characteristics
V
= 2.0V to 6.0V, CL = 50 pF, tr = t
CC
Symbol Parameter Conditions
t
, t
PHL
Maximum Propagation 2.0V 55 95 120 145 ns
PLH
Delay 4.5V 11 19 24 29 ns
t
, t
TLH
Maximum Output Rise 2.0V 30 75 95 110 ns
THL
and Fall Time 4.5V 8 15 19 22 ns
C
PD
Power Dissipation (per gate) 20 pF
Capacitance (Note 5)
C
IN
Maximum Input 5 10 10 10 pF
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD = CPD V
= CPDVCCf + ICC.
I
S
= 6 ns (unless otherwise specified)
f
V
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Typ Guaranteed Limits
6.0V 9 16 20 24 ns
6.0V 7 13 16 19 ns
2
f + ICC VCC, and the no load dynam ic current consum pt ion,
CC
Guaranteed
Limit
MM74HC04
Units
Units
3 www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
MM74HC04
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Small Outline Package ( SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14A
Package Number M14D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
MM74HC04
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
5 www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
MM74HC04 Hex Inverter
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the
user.
Package Number N14A
2. A critical component in any compon ent of a lif e supp ort
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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