Fairchild KA3012D service manual

KA3012D

4-Channel Motor Driver

www.fairchildsemi.com

Features

• BTL (H-Bridge type linear) 4channel motor driver

• Wide dynamic range:

-SV

-SV

• Built in level-shift circuit

• Built in OP-amp for digital input

• Built in thermal shutdown (TSD) circuit

• Three independent sources

• Low crossover distortion

• Built-in reverse rotation prevented

• Built-in short breaker

=12V, PV

CC

=12V, PV

CC

=5V, RL=8Ω → VOM=4.2V

CC1

=12V, RL=24Ω → VOM=10.4V

CC2

Description

The KA3012D is a monolithic IC, and suitable for 4-CH
motor driver which drives sled motor, loading motor, focus
& tracking actuator of CD-media system and built in OP­amp which can receive digital signal from servo of CD­media system.

28-SSOPH-375

Typical Applications

• Compact disk R O M (CD-ROM)

• Compact disk RW (CD-RW)

• Digital video disk ROM (DVD-ROM)

• Digital video disk RAM (DVD-RAM)

• Digital video disk player (DVDP)

• Other compact disk media

©2000 Fairchild Semiconductor International

Ordering Information

Device Package Operating Temp.

KA3012D-02 28-SSOPH-375 -35 °C ~ 85 °C

KA3012D-02TF 28-SSOPH-375 -35 °C ~ 85 °C

Rev. 1.0.1

February. 2000.

1

Pin Assignments

GND

CH4-O

1234567 891011121314

CH1-O

CH1-O

KA3012D

FIN

CH4-O

AMP4-O

AMP4-I (−)

AMP4-I (+)

PVCC1

(GND)

PVCC2

AMP3-I (+)

AMP3-O

AMP3-I (−)

CH3-O

CH3-O

GND

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KA3012D

FIN

SVCC

(GND)

BIAS

AMP1-O

AMP1-I (−)

AMP1-I (+)

GND

MUTE

CH2-O

AMP2-O

AMP2-I (−)

AMP2-I (+)

CH2-O

2

KA3012D

Pin Definitions

Pin Number Pin Name I/O Pin Function Description

1 CH1-O O Drive CH 1 output (−)
2 CH1-O O Drive CH 1 output (+)
3 AMP1-O O Op-amp CH 1 output
4AMP1-I(−) I Op-amp CH 1 input (−)
5 AMP1-I(+) I OP-amp CH 1 input (+)
6 BIAS I Bias input
7 SVCC - Supply voltage (Signal)
8 GND - Ground

9MUTEIMute
10 AMP2-I(+) I OP-amp CH 2 input (+)
11 AMP2-I(−) I Op-amp CH 2 input (−)
12 AMP2-O O Op-amp CH 2 output
13 AMP2-O O OP-amp CH 2 output (+)
14 CH2-O O Op-amp CH 2 output

(Op-amp CH 2 output)
15 GND - Ground
16 CH3-O O Drive CH 3 output (−)
17 CH3-O O Drive CH 3 output (+)
18 AMP3-O O OP-amp CH 3 output
19 AMP3-I(−) I Drive CH 3 input (−)
20 AMP3-I(+) I Drive CH 3 input (+)
21 PVCC2 - Supply voltage (CH 2 & CH 3)
22 PVCC1 - Supply voltage (CH1 & CH 4)
23 AMP4-I(+) I OP-amp CH 4 input (+)
24 AMP4-I(−) I Op-amp CH 4 input (−)
25 AMP4-O O Op-amp CH 4 output
26 CH4-O O Drive CH 4 output (+)
27 CH4-O O Drive CH 4 output (−)
28 GND - Ground

3

Internal Block Diagram

KA3012D

PVCC1

AMP4-I (+)

AMP4-I (−)

+

10k10k

AMP4-O

CH4-O

PV

10k

BIAS

CC1

+

−

SV

SVCC

−

PV

+

AMP1-O

10k10k

CC1

AMP1-I (−)

− +

−

+

10k

/2

−

+

+

−

10k

10k

AMP1-I (+)

CH4-O

GND

10k 10k

GND

PV

CC1

PV

CC1

10k 10k

1234567 891011121314

CH1-O

+−+

/2

−

LEVEL-SHIFT

LEVEL-SHIFT

−

/2

−−

++

CH1-O

NOTE:

The drive channel outputs are determined pre OP-amp output.

GND

TSD

CC

GND

PV

GND

PVCC2

CC2

GND

AMP3-I (+)

10k

−

+

10k

MUTE

+

20k

20k

MUTE

AMP3-I (−)

10k 10k

++

PV

CC2

+

−

AMP2-I (−)

AMP2-I (+)

−−

/2

+

LEVEL-SHIFT

LEVEL-SHIFT

+

PV

/2

CC2

10k

−

10k

AMP2-O

−

+

−

10k10k

PV

−

−

PV

++

CH2-O

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GND

CC2

CC2

−

/2

/2

10k10k

CH2-O

GND

CH3-O

CH3-O

AMP3-O

4

KA3012D

Equivalent Circuits

Op-amp input Op-amp output

5, 10, 20, 23
Pin

10kΩ

1kΩ

80Ω

AMP-I (−)AMP-I (+)
4, 11, 19, 24

Pin

80Ω

Drive output Bias

10kΩ

CH-O
(2, 13, 17, 26 Pin)

CH-O
(1, 14, 16, 27 Pin)

Bias
(6 Pin)

Mute

AMP-O
3, 12, 17, 25 Pin

200Ω

Mute
(9 Pin)

50k

50k

5

Absolute Maximum Rating (Ta = 25°C)

Parameter Symbol Value Unit

Supply voltage V
Power dissipation P
Operating temperature range T
Storage temperature range T

CC

D
OPR
STG

NOTE:

1. When mounted on 50mm × 50mm × 1mm PCB (Phenolic resin material).

2. Power dissipation reduces 13.6mW / °C for using above Ta=25°C.

3. Do not exceed P

and SOA (Safe operating area).

D

15 V

note

1.7

−35 ~ +85 °C

−55 ~ +150 °C

Power Dissipation Curv e

Pd (mW)

3,000

2,000

KA3012D

W

1,000

0

0 25 50 75 100 125 150 175

SOA

85

Recommended Operating Condition (Ta = 25°C)

Parameter Symbol Min. Typ. Max. Unit

, V

Supply voltage SV

CC

CC1

V

CC2

,

4.5 - 13.2 V

Ambient temperature, Ta [°C]

6

KA3012D

Electrical Characteristics

(Ta=25°C, V

CC1=VCC2

Parameter Symbol Conditions Min. Typ. Max. Units

DRIVE CIRCUIT

Quiescent current 1 I
Quiescent current 2 I
Output offset voltage 1 V
Output offset voltage 2 V
Max.output amplitude 1 V
Max.output amplitude 2 V
Voltage gain 1 G

Voltage gain 2 G

Mute on voltage V
Mute off voltage V

INPUT OP-AMP CIRCUIT

Input offset voltage V
Input bias current I
High level output voltage V
Low level output voltage V
Output driving current sink I

Output driving current source I

Slew rate SR 100kHz square-wave 2Vp-p output - 1 - V / µs

=5V, RL=8Ω)

CC1
CC2

OO1
OO2
OM1
OM2

VC1

VC2

Mon

Moff

OFOP
BOP

OHOP

OLOP
SINK

SOURCE

No load, Mute off - 15 20 mA
No load, Mute on - - 500 uA
CH 1, CH 4 −70 0 70 mA
CH 2, CH 3 −90 - 90 mV
CH 1, CH 4 3 4.2 - V
CH 2, CH 3 (RL=24Ω) 8 10.4 - V
VIN=0.1V

, 1kHz, sinewave.

RMS

10 12.0 14 dB
Input OP-amp
→ Buffer CH 1, CH 4

VIN=0.1V

, 1kHz, sinewave.

RMS

16 18 20 dB
Input OP-amp
→ Buffer CH 2, CH 3

-2.0--V

---0.5V

- −10 0 10 mV

- - - 300 nA

- 10 10.9 - V

--1.11.8V

Input op-amp output

& 1.2kΩ

→ V

CC

Input op-amp output

1--mA

1--mA

→ GND & 1.2kΩ

7

Application Information

1. MUTE

KA3012D

Pin #9 Mute circuit

High Turn-on

Low Turn-off

9

Output driver
bias

Open Turn-off

• When the voltage level of the mute pin is above 2V, the mute circuit is activated so that the output circuit will be
muted.

• When the mute pin #9 is open or the voltage of the mute pin #9 is below 0.5V, the mute circuit is deactivated and the output
circuit operates normally.

• When the mute circuit is activated, the voltage level of output pins becomes 1/2V

(approximately).

CC

2. TSD (THERMAL SHUTDOWN)

V

REF BG

Output driver

R11

R12

bias

Q11

• If the chip temperature rises above 175°C, then the TSD (Thermal shutdown) circuit is activated and the output circuit is
muted.

•The V

is the output voltage of the band-gap-referenced bias in circuit and acts as the input voltage of the TSD

REF BG

circuit.

• The base-emitter voltage of the TR,Q11 is designed to turn-on at 460mA.
V

BE

= V

REF BG

× R12 / (R11 + R12)=460m V

• When the chip temperature rises up to 175°C, the turn-on volt a g e of the Q11 drops down to 460 mV. (Hysteresis: 25°C) and
Q11 turns on so the output circuit is muted.

8

KA3012D

3. DRIVER

+∆I

Buffer

−∆I

+

−

Buffer

+

−

−∆V+∆V

Q1

CH-O
(1, 14,
16, 27 Pin)

Q3

M

CH-O
(2, 13,
17, 26 Pin)

Q2

Q4

AMP-I (+)
(5, 10, 20, 23 Pin)
AMP-I (−)
(4, 11, 19, 24 Pin)

AMP-O
(3, 12, 18, 25 Pin)

Pre-amp

+

−

BIAS
(6 Pin)

10k

AMP

+

−

10k

Level
shift

• The gain of pre-op. Amplifier can be changed by manipulating amp input resistor or feedback resistor.

• The voltage, V

, is the reference voltage given by the bias voltage of the pin #6.

REF

• The level shift produces the current due to the difference between the pre amp output signal and the arbitrary reference
(bias) signal. (The current produced as +∆I and −∆I is fed into the driver buffer. (CH1/CH4)
The current produced as +2∆I and −2∆I is fed into the driver buffer. (CH2/CH3)

• Driver buffer drives the power TR of the output stage according to the state of the input signal.

• The output stage is the BTL driver and the motor is rotating in forward direction by operating TR Q1 and TR Q4.On the
other hand, if TR Q2 and TR Q3 is operating, the motor is rotating in reverse direction.

• When the output voltage of Pre-Amp (Pin 3, 12, 18, 25) is below the V

• When the output voltage of Pre-Amp (Pin 3, 12, 18, 25) is above the V

•The gain (A

AV20 log

A

V

) of the drive circuit is as follows.

V

4V

IN

20 log

------------

V

4V

------------

V

IN

IN

IN

12 dB() (CH1/CH4)==

18 dB() (CH1/CH4)==

, then the direction of the motor is in forward.

REF

, then the direction of the motor in reverse.

REF

4. CONNECT A BY-PASS CAPACITOR, 0.1µµµµF BETWEEN THE SUPPLY VOLTAGE SOURCE.

V

CC1

7

104

5. RADIATION FIN IS CONNECTING TO THE INTERNAL GND OF THE PACKAGE.

CONNECT THE FIN TO THE EXTERNAL GND.

9

KA3012D

Typical Performa n ce Cha ra cte ristic s

VCC vs ICC (No load)

14

12

10

8

6

ICC (mA)

4

2

0

0246 810121416

AMP-I (+) vs OUTPUT VOLTAGE

Figures can be obtained by changing of AMP-I (+) from 0V to 5V, shows the voltage difference between CH-O and CH-O.
(AMP-I (+) and AMP-O are shorted.)

VCC (V)

1. CH 1 and CH 4 (12dB) 2. CH 2 and CH 3 (18dB)

Output Voltage Vom1(V)

-10

-12

12
10

8
6
4
2
0

-2

-4

-6

-8

0

12345

5
4
3
2
1
0

-1

-2

Output Voltage Vom1(V)

-3

-4

-5
012 453

AMP-I (+)(V) AMP-I (+)(V)

VCC vs Gain

1. CH 1 and CH 4 (12dB) 2. CH 2 and CH 3 (18dB)

15

14

13

12

Gain1(dB)

11

21

20

19

18

Gain1(dB)

17

10

9

4

56789

16

011121314 4

VCC (V) VCC (V)

15

56789

10

011121314

KA3012D

Test Circuits

V

’

R

R

L4

SW4

10µF

OPOUT

PV

CC1

OPIN (+)

OPIN (−)

10µF

PV

CC2

OPIN (+)

OPIN (−)

OPOUT

L3RL3

V

SW3

1516171819202122232425262728

KA3012D

1234567 891011121314

SW1

OPOUT

OPIN (−)

OPIN (+)

10µF

V

IN5

A

CC

10µF

1

1MΩ

3

2

V

IN4

SV
12V

SW6

V

R

L1

OPIN (+) OPIN (−)OPOUT

SW5

3

1

1MΩ

2

V

IN2

V

V

IN1

Bias

2.5V

V

V

IN3

OPIN (+)

V

MUTE

V

OPOUT

OPIN (−)

R

1.2kΩ

V

SW2

RL2’

L2

1

V

3

V

CC

SW7

2

11

Typical Application Circuits

SERVO PREA M P MICOM

FOCUS TRACKING BIAS SLED

10kΩ

10kΩ

LOADING
(SPINDLE)

KA3012D

MUTE

M

10kΩ

GND

10kΩ

1516171819202122232425262728

KA3012D

1234567 891011121314

GND

10kΩ

10kΩ

10kΩ

M

10kΩ

BIAS

12

KA3012D

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURT HER NOTICE TO ANY
PRODUCTS HEREI N TO IMPROVE RELIABILITY, FUNCTIO N OR DESIGN. FAIRCH IL D DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER IT S PATENT RIGHTS, NOR THE RIGHTS OF OTHE RS.

LIFE SUPPORT POL I CY

FAIRCHILD’S PR ODUCTS ARE NOT AUTH ORIZED FOR USE AS C RITICAL COMPONENT S IN LIFE SUPPORT DE VICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
INTERNATIONAL. As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with

2. A critical component in any component of a life support
device or sy stem whose fai lure to perform can be
reasonably expec ted to cause the failur e of the life support
device or system, or to affect its safety or effec t iv ene ss .

instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

www.fairchildsemi.com

12/1/00 0.0m 001

 2000 Fairchild Semiconductor International

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