Fairchild ILC5061 service manual
V
REF
V
OUT
V
SS
V
IN
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ILC5061
Power Supply reset Monitor with 1% Precision
Features
• All-CMOS design in SOT-23 or SC70 package
• ±1% precision in Reset Detection
• Only 1µA of Iq
• 2mA of sink current capability
• Built-in hysteresis of 5% of detection voltage
• Voltage options of 2.6, 2.9, 3.1, 4.4, and 4.6V fit most
supervisory applications
• Open-Drain Reset Output
Applications
• Microprocessor reset circuits
• Memory battery back-up circuitry
• Power-on reset circuits
• Portable and battery powered electronics
Block Diagram Pin Package Configurations
Description
All-CMOS Monitor circuits in either a 3-lead SOT-23 or
SC70 package offer the best performance in power consumption and accuracy.
The ILC5061 comes in a s eries o f ±1% accu rate trip voltages
to fit most microprocessor applications. Even thou gh its output can sink 2mA, the device draws only 1µA in normal
operation.
Additionally, a built-in hysteresis of 5% of detect voltage
simplifies system design.
Top View
1
V
OUT
3
V
SC-70
2
V
SS
IN
1
V
OUT
3
V
SOT-23
2
V
SS
IN
Rev. 2.5 1/2/03
ILC5061 PRODUCT SPECIFICATION
ILC5061
Absolute Maximum Ratings
Parameter Symbol Ratings Units
Input Voltages V
Output Current I
Output Voltages V
Continuous Total
SOT 23 P
Power Dissipation
Operation Ambient temperature T
Storage Temperature T
IN
OUT
OUT
opr
stg
VSS-0.3~+VIN+03 V
d
12 V
50 mA
150 mW
-30~+80
-40~+125
o
C
o
C
Electrical Characteristics T
Parameter Symbol Conditions Min Type Max Units
Detect Fail Voltage V
Hysteresis Range V
Supply Current I
Operating Voltage V
Output Current I
Temperature Charac-
DV
teristics
Delay Time Release
Voltage Output Inversion)
Note:
1. An additional resistor between the V
to increasing V
DR.
DF
HYS
SS
IN
OUT
/(DT
DF
opr
T
DLY
(VDR to V
inversion)
*
OUT
= 25°C
A
VDF X 0.99 V
DF
VDF X 1.01 V
VDF X 0.02 VDF X 0.05 VDF X 0.08 V
V
IN
V
IN
V
IN
V
IN
V
IN
= 1.5V
= 2.0V
= 3.0V
= 4.0V
= 5.0V
0.9
1.0
1.3
1.6
2.0
2.6
3.0
3.4
3.8
4.2
µA
VDF = 2.1~ 6.0V 1.5 10.0 V
N-ch VDS = 0.5V
V
= 1.0V
IN
V
= 2.0V
IN
V
= 3.0V
IN
V
= 4.0V
IN
V
= 5.0V
IN
VDF)
-30oC<T
opr
<80oC
-200 +100 +200
pin and supply voltage may cause deterioration of the characteristics due
IN
2.2
7.7
10.1
11.5
13.0
mA
Ppm/
0.1 ms
o
C
2 Rev. 2.5 1/2/03
PRODUCT SPECIFICATION ILC5061
Functional Description
The following designators 1~6 refer to the timing diagram below.
1. While the input voltage ( V
state.
2. When the input V
voltage falls lower than VDF, V
IN
3. If the input voltage further decr eases below the minimu m operating voltage (V
unstable. In this condition, if the V
4. During an increase o f the i nput v oltage fr om the V
Exceeding that level , the outp ut s tay s a t the gr ound lev el ( V
and the detect release voltage (V
5. If the input voltage increases more than V
6. The difference between V
) is higher than the d etect voltag e (VDF), the V
IN
drops near to ground voltage
OUT
pin is pulled up, V
OUT
voltage, V
SS
).
DR
, then the V
DR
and VDF is the hysteresis in the system.
DR
indicates the VIN voltage.
OUT
is not stable i n the vo ltag e belo w the V
OUT
) between the minimum o per ati ng voltag e ( V
SS
output pin is at high impedance state.
OUT
output pin is at hig h impedance
OUT
MIN
), the V
output becomes
OUT
MIN
MIN
.
)
INPUT VOLTAGE (V
DETECT RELEASE VOLTAGE (V
6
DETECT FAIL VOLTAGE (V
MINIMUM OPERATING VOLTAGE (V
GROUND VOLTAGE (V
OUTPUT VOLTAGE (V
GROUND VOLTAGE (V
1
2
3
4
5
IN)
SS)
OUT)
SS)
DR)
DF)
MIN)
Rev. 2.5 1/2/03 3
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